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參數(shù)資料
| 型號： | LC72715PW |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, SQFP-64 |
| 文件頁數(shù)： | 5/26頁 |
| 文件大小： | 167K |
| 代理商： | LC72715PW |
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LC72715PW
No.A1650-13/26
Symbol
Parameter
min
typ
max
unit
tSARD
Address and CS to RD setup
20
ns
tHARD *1
RD to address and CS hold
0
ns
tWRDL
RD “L” level width
340
ns
tCYRD
RD cycle wait
150
ns
tWRDY
RDY width (at register output)
60
210
ns
tRDH
RD data hold
0
40
ns
tSAWR
Address and CS to WR setup
20
ns
tHAWR
WR to address and CS hold
20
ns
tCYWR
WR cycle wait
150
ns
tWWRL
WR “L” level width
200
ns
tWDS
WR data setup
20
ns
tWDH
WR data hold
20
ns
tDRDY
RDY output delay
0
40
ns
tDRDY2
RDY output delay 2
0
40
ns
RD width at output of corrected data
BUSWD=L (8bit)
340
ns
tWDRD
RD width at output of corrected data
BUSWD=H (16bit)
620
ns
RDY width at output of corrected data
BUSWD=L (8bit)
60
210
ns
tWDRDY
RDY width at output of corrected data
BUSWD=H (16bit)
300
490
ns
tRDDM
DMA start time
20
ns
tDREQ
DACK to DREQ delay
260
ns
tDATON
DATn output start time
0
40
ns
tDDATn
DATn output delay
0
40
ns
tCYDM
DMA cycle wait
420
ns
tWRDM
RD “L” level width at DMA transmission output
300
ns
*1 Specified up to the earliest negating of A0 to A3 and CS
tDREQ
tCYDM
tRDH
DACK (when DACK is selected)
RD (default)
D(n)
DREQ
tWRDM
A0 to A3
CS
VALID
OUTPUT
tDDATn
tRDDM
tSARD
tHARD
VALID
OUTPUT
0
*A0 to A3 should be set to 0
during DMA transmission
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