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參數資料
| 型號： | LC72715PW |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, SQFP-64 |
| 文件頁數： | 14/26頁 |
| 文件大?。?/td> | 167K |
| 代理商： | LC72715PW |
LC72715PW
No.A1650-21/26
(2) Error-corrected Data Output Timing (Basic Restrictions)
Data received by LSI is corrected error and written sequentially without any interruption into the output data buffer
memory. Since this data buffer memory has a capacity for one-block data, the corrected data before reading is over-
written by the next data if data read is delayed. In consequence, it is essential to read data according to the timing
stipulations shown below.
This LSI specifies the output timing for each of horizontally and vertically corrected data as follows:
Upon completion of preparation for the output data, LSI lowers the INT pin to “L” as a request for transmission.
Data output has the period during which only horizontal data can be read and the period during which horizontal and
vertical data are read according to the time division.
Complete data transmission within about 9ms after INT = “L”. When only the horizontally-corrected data can be
output, data transmission is possible for about 18ms. Even when CPU is in the course of reading, the output buffer is
overwritten by the next output data once the specified time period is expired.
The data amount that can be read by one horizontal and vertical transmission request (INT) is one block only.
Vertically-corrected data is output sequentially beginning with the first block after completion of vertical correction,
but the data of parity block is not output.
Horizontal data output period
Horizontal data output
period
Vertical data output
period
Period during which data guarantee is impossible
Output of only horizontal data
Divided output for horizontal and
vertical data
1ms
18ms
68
μs
68
μs
INT
1ms
9ms
INT
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