參數(shù)資料
型號(hào)： LH540215
廠商： Sharp Corporation
英文描述： 512 x 18 / 1024 x 18 Synchronous FIFO
中文描述： 512 ×一千〇二十四分之一十八× 18同步FIFO
文件頁(yè)數(shù)： 12/48頁(yè)
文件大?。?/td> 423K
代理商： LH540215
Table 3. Selection of Read and Write Operations
LD
WEN
3,4
REN
3, 4
WCLK
RCLK
ACTION
L
X
X
–
–
No operation.
L
L
L
∧
∧
Illegal combination, which will cause errors.
Write to a programmable register.
1
L
L
H
∧
X
L
H
H
∧
X
Hold present value of programmable-register write counter, and do not
write.
Read from a programmable register.
1
L
H
L
X
∧
L
H
H
X
∧
Hold present value of programmable-register read counter, and do not
read.
2
H
L
X
∧
X
Normal FIFO write operation.
H
X
L
X
∧
Normal FIFO read operation.
H
L
X
–
X
No write operation.
H
H
X
X
X
No write operation.
H
X
L
X
–
No read operation.
H
X
H
X
X
No read operation.
H
L
L
–
–
No operation.
KEY:
H = Logic ‘HIGH’; L = Logic ‘LOW’; X = ‘Don’t-care’ (logic ‘HIGH,’ logic ‘LOW,’ or any transition);
∧
= A ‘LOW’-to-‘HIGH’ transition; – = Any condition EXCEPT a ‘LOW’-to-‘HIGH’ transition.
NOTES:
1.
The selection of a programmable register to be written or read is controlled by two simple state machines. One state machine controls the se-
lection for writing; the other state machine controls the selection for reading. These two state machines operate independently of each other.
Both state machines are reset to point to Word 0 by a reset operation.
In the Enhanced Operating Mode, if Control Register bit 00 is set,
both state machines are also reset to point to Word 0 by deassertion of LD after LD has been asserted (that is, by a rising edge of
LD), followed by a valid memory array write cycle for the writing-control state machine and/or by a valid memory array read cycle
for the reading-control state machine.
2.
The order of the two programmable registers which are accessible in IDT-Compatible Operating Mode, as selected by either state machine, is
always:
Word 0: Almost-Empty Offset Register
Word 1: Almost-Full Offset Register
Word 0: Almost-Empty Offset Register
...
(repeats indefinitely)
...
The order of the three programmable registers which are accessible in Enhanced Operating Mode, as selected by either state
machine, is always:
Word 0: Almost-Empty Offset Register
Word 1: Almost-Full Offset Register
Word 2: Control Register
Word 0: Almost-Empty Offset Register
…
(repeats indefinitely)
…
Note that, in IDT-Compatible Operating Mode, Word 2 is not accessed; Word 0 and Word 1 alternate.
After normal FIFO operation has begun, writing new contents into either of the offset registers should only be done when the FIFO is empty.
WEN
, REN
, and OE may be ANDed terms in the enabling of read and write operations, according to the state of the EMODE control
input and of Control Register Bit 05.
3.
4.
BOLD ITALIC = Enhanced Operating Mode
LH540215/25
512 x 18/1024 x 18 Synchronous FIFO
12
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