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參數(shù)資料
| 型號： | LH540215 |
| 廠商： | Sharp Corporation |
| 英文描述： | 512 x 18 / 1024 x 18 Synchronous FIFO |
| 中文描述： | 512 ×一千〇二十四分之一十八× 18同步FIFO |
| 文件頁數(shù)： | 44/48頁 |
| 文件大?。?/td> | 423K |
| 代理商： | LH540215 |
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The GAL20RA10B and GAL22V10C PLDs each pro-
vide ten macrocells. One macrocell may be configured to
operate as a simple inverting or non-inverting buffer, a
simple NAND or AND gate, an AND-OR gate, or a flipflop
with an AND-OR input structure. The GAL20RA10B
macrocell architecture in particular supports the imple-
mentation of an asynchronous-set/reset clocked D flipflop
like the one shown in Figure 29b, except for some polarity
differences at certain points within the logic diagram. If a
slower implementation of the final AND gate can be
tolerated in a given application, a single GAL20RA10B
may be used to implement the circuit of Figure 29b five
times, thus allowing for a cascade six FIFOs deep, with
no second PLD being necessary. The GAL20RA10B and
GAL22V10C PLDs are manufactured by Lattice Semi-
conductor Corporation, 5555 Northeast Moore Court,
Hillsboro, OR 97124, USA.
Width Expansion Along With Depth Cascading
In principle, width expansion may be used with either
of the two possible depth-cascading schemes.
However, when using the token-passing depth-cas-
cading scheme, width expansion reduces simply to plac-
ing two or more cascades in parallel. In this mode of
interconnection, no architectural support is available for
interlocked-paralleled operation. Composite-flag logic
may, of course, be designed to fit any complete array
configuration, to determine meaningful full and empty
indications for the entire array. This logic may, for in-
stance, OR the FF and EF signals from the devices at the
same relative position in each of the paralleled cascades,
and then AND all of the rank-FF signals together; and
likewise for all of the rank-EF
signals. Then, the entire
array is indicated to be full, if all ranks of devices (across
the paralleled cascades) are individually full; and, simi-
larly for empty.
When using the pipelined depth-cascading scheme,
on the other hand, the first rank of devices (the one which
receives input data words from the external system) and
the last rank of devices (the one which provides output
data words to the external system) may be operated in an
interlocked-paralleled manner. Figure 30 shows a sug-
gested interconnection scheme for two paralleled cas-
cades, each three devices deep. The entire array of
Figure 30 would comprise a 3072
×
36 ‘effective FIFO,’ if
implemented with 1024
×
18 LH540225 devices. When-
ever the number of paralleled cascades exceeds two, a
small amount of external logic is necessary to implement
the interlocking.
CK
D
Q
AS
TRANSFER
CLOCK
AR
WEN
(DEVICE n)
FF
(DEVICE n)
EF
(DEVICE n-1)
RESET
NOTES:
1. AS sets Q=1 regardless of CK or D. (Asynchronous Set.)
AR sets Q=0 regardless of CK or D. (Asynchronous Reset.)
2. Q=0 occurs if and only if device n-1 goes completely
empty and device n goes completely full. Q=0 is
maintained as long as these conditions persist.
3. This circuit is used as block 'A' in Figure 29a and in
Figure 30.
BOLD ITALIC = Enhanced Operating Mode.
540215-31
Figure 29b. External Logic Needed for
TI-Style Pipelined Depth Cascading
BOLD ITALIC = Enhanced Operating Mode
LH540215/25
512 x 18/1024 x 18 Synchronous FIFO
44
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| LH540235 | 2048 x 18 / 4096 x 18 Synchronous FIFOs |
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| LH5424-S | 5 mm T1 3/4 LED, Non Diffused Super-Bright, Hyper-Red GaAIAs-LED |
| LH5424-QT | 5 mm T1 3/4 LED, Non Diffused Super-Bright, Hyper-Red GaAIAs-LED |
| LH5424-T | 5 mm T1 3/4 LED, Non Diffused Super-Bright, Hyper-Red GaAIAs-LED |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LH540215U-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| LH540215U-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| LH540215U-25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| LH540215U-35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| LH540215U-50 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
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