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參數(shù)資料
| 型號： | LH540215 |
| 廠商： | Sharp Corporation |
| 英文描述： | 512 x 18 / 1024 x 18 Synchronous FIFO |
| 中文描述： | 512 ×一千〇二十四分之一十八× 18同步FIFO |
| 文件頁數(shù)： | 8/48頁 |
| 文件大?。?/td> | 423K |
| 代理商： | LH540215 |
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PIN
NAME
PIN
TYPE
1
DESCRIPTION
WXO/HF
Write
Expansion
Output/
Half-Full Flag
O
This signal is dual-purpose; its functionality is determined during a reset operation
according to the states of the two control inputs WXI/
WEN
2
and RXI/
REN
2
. (See
Tables 1 and 2.) In the standalone or paralleled configuration, whenever
HF is LOW
the device is more than half full. In IDT-Compatible Operating Mode, HF is
asynchronous;
in the Enhanced Operating Mode, HF may be synchronized
either to WCLK or to RCLK after a reset operation, according to the state of
Control Register bits 02 and 03. (See Table 5.)
In the IDT-compatible cascaded
configuration, a pulse is sent from WXO to the WXI input of the next FIFO in the
daisy-chain cascade, whenever the last location in the FIFO is written.
When PAE is LOW, the FIFO is ‘a(chǎn)lmost empty,’ based on the almost-empty-offset
value programmed into the FIFO’s Almost-Empty Offset Register. The default value
of this offset at reset is one-eighth of the total number of words in the FIFO-memory
array, minus one, measured from ‘empty.’ (See Table 4.) In IDT-Compatible
Operating Mode, PAE is asynchronous.
In the Enhanced Operating Mode, PAE
is synchronized to RCLK after a reset operation, according to the state of
Control Register bit 01. (See Table 5.)
When EF is LOW, the FIFO is empty; further advancement of its internal read-
address pointer, and further readout of data words from its internal memory array to
its Data Outputs, are inhibited. When EF is HIGH, the FIFO is not empty. EF is
synchronized to RCLK.
This signal is dual-purpose; its functionality is determined by the state of the
EMODE
control input during a reset operation. (See Tables 1 and 2.) In the IDT-
Compatible Operating Mode, in a cascaded configuration, a pulse is sent from RXO
to the RXI input of the next FIFO in the daisy-chain cascade, whenever the last
location of the FIFO is read.
In the Enhanced Operating Mode, whenever
EMODE is being asserted (LOW), EF
2
behaves as an exact duplicate of EF,
but delayed by one full cycle of RCLK with respect to EF.
Data outputs to drive an 18-bit bus.
+5 V power-supply pins.
0 V ground pins.
PAE
Programmable
Almost-Empty
Flag
O
EF
Empty Flag
O
RXO
/EF
2
Read
Expansion
Output
O
Q
0
– Q
17
V
CC
V
SS
Data Outputs
Power
Ground
O/Z
V
V
NOTE:
1.
I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level
PIN DESCRIPTIONS (cont’d)
BOLD ITALIC = Enhanced Operating Mode
LH540215/25
512 x 18/1024 x 18 Synchronous FIFO
8
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相關(guān)代理商/技術(shù)參數(shù) |
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| LH540215U-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
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| LH540215U-25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| LH540215U-35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
| LH540215U-50 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous FIFO |
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