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| 型號(hào)： | LM3S101 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁(yè)數(shù)： | 46/284頁(yè) |
| 文件大?。?/td> | 1774K |
| 代理商： | LM3S101 |
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LM3S101 Data Sheet
March 22, 2006
46
Preliminary
Brown-out resets are controlled with the
Power-On and Brown-Out Reset Control (PBORCTL)
register (see page 60). The
BORIOR
bit in the
PBORCTL
register must be set for a brown-out to
trigger a reset. The brown-out reset sequence is as follows:
1.
When V
DD
drops below V
BTH
, an internal BOR condition is set.
If the
BORWT
bit in the
PBORCTL
register is set, the BOR condition is resampled sometime
later (specified by
BORTIM
) to determine if the original condition was caused by noise. If the
BOR condition is not met the second time, then no action is taken.
2.
3.
If the BOR condition exists, an internal reset is asserted.
4.
The internal reset is released and the controller fetches and loads the initial stack pointer, the
initial program counter, and the first instruction designated by the program counter, and then
begins execution.
5.
The internal
BOR
signal is released after 500
μ
s to prevent another BOR condition from being
set before software has a chance to investigate the original cause.
The internal Brown-Out Reset timing is shown in Figure 17-10 on page 280.
6.1.2.5
Software Reset
Each peripheral can be reset by software. There are three registers that control this function (see
the
SRCRn
registers, starting on page 62). If the bit position corresponding to a peripheral is set,
the peripheral is reset. The encoding of the reset registers is consistent with the encoding of the
clock gating control for peripherals and on-chip functions (see “System Control” on page 49).
Writing a bit lane with a value of 1 initiates a reset of the corresponding unit. Note that all reset
signals for all clocks of the specified unit are asserted as a result of a software-initiated reset.
The entire system can be reset by software also. Setting the
SYSRESETREQ
bit in the Cortex-M3
Application Interrupt and Reset Control
register resets the entire system including the core.
The software-initiated system reset sequence is as follows:
1.
A software system reset in initiated by writing the
SYSRESETREQ
bit in the ARM Cortex-M3
Application Interrupt and Reset Control
register.
2.
An internal reset is asserted.
3.
The internal reset is released and the controller fetches and loads the initial stack pointer, the
initial program counter, and the first instruction designated by the program counter, and then
begins execution.
The software-initiated system reset timing is shown in Figure 17-11 on page 281.
6.1.2.6
Watchdog Timer Reset
The watchdog timer module's function is to prevent system hangs. The watchdog timer can be
configured to generate an interrupt to the controller on its first time-out, and to generate a reset
signal on its second time-out.
After the first time-out event, the 32-bit counter is reloaded with the value of the
Watchdog Timer
Load (WDTLOAD)
register (see page 163), and the timer resumes counting down from that value.
If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the
reset signal has been enabled, the watchdog timer asserts its reset signal to the system. The
watchdog timer reset sequence is as follows:
1.
The watchdog timer times out for the second time without being serviced.
2.
An internal reset is asserted.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LM3S101_0610 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| LM3S101-CRN20 | 功能描述:ARM微控制器 - MCU MICROCONTROLLER RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| LM3S101-CRN20-XNPP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| LM3S101-CRN20-XNPR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| LM3S101-CRN20-XNPT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
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