參數(shù)資料
型號(hào): M25PE40VMN6G
廠商: 意法半導(dǎo)體
元件分類(lèi): DRAM
英文描述: 4 Mbit Uniform Sector, Serial Flash Memory
中文描述: 4兆位統(tǒng)一部門(mén),串行閃存
文件頁(yè)數(shù): 44/60頁(yè)
文件大?。?/td> 315K
代理商: M25PE40VMN6G
Reset
M25PE40
44/60
8
Reset
Driving Reset (Reset) Low while an internal operation is in progress will affect this operation
(write, program or erase cycle) and data may be lost.
All the Lock bits are reset to 0 after a Reset Low pulse.
Table 12
shows the status of the device after a Reset Low pulse.
Table 12.
Device status after a Reset Low pulse
Conditions:
Reset pulse occurred
Lock bits status
Internal logic
status
Addressed data
While decoding an instruction
(1)
: WREN,
WRDI, RDID, RDSR, READ, RDLR,
Fast_Read, WRLR, PW, PP, PE, SE, BE,
SSE, DP, RDP
1.
S remains Low while Reset is Low.
Reset to 0
Same as POR
Not significant
Under completion of an Erase or Program
cycle of a PW, PP, PE, SSE, SE, BE
operation
Reset to 0
Equivalent to
POR
Addressed data
could be modified
Under completion of a WRSR operation
Reset to 0
Equivalent to
POR (after t
W
)
Write is correctly
completed
Device deselected (S High)
and
in Standby
mode
Reset to 0
Same as POR
Not significant
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