參數(shù)資料
型號: M25PE40VMN6G
廠商: 意法半導(dǎo)體
元件分類: DRAM
英文描述: 4 Mbit Uniform Sector, Serial Flash Memory
中文描述: 4兆位統(tǒng)一部門,串行閃存
文件頁數(shù): 49/60頁
文件大?。?/td> 315K
代理商: M25PE40VMN6G
M25PE40
DC and AC parameters
49/60
Table 19.
AC characteristics (33 MHz operation)
33MHz only available for products marked since week 40 of 2005
(1)
Test conditions specified in
Table 14
and
Table 15
Symbol
Alt.
Parameter
Min.
Typ.
Max.
Unit
f
C
f
C
Clock Frequency for the following
instructions: FAST_READ, PW, PP, PE, SE,
DP, RDP, WREN, WRDI, RDSR
D.C.
33
MHz
f
R
Clock Frequency for READ instructions
D.C.
20
MHz
t
CH (2)
t
CL (2)
t
CLH
Clock High Time
13
ns
t
CLL
Clock Low Time
13
ns
Clock Slew Rate
2
(peak to peak)
0.1
V/ns
t
SLCH
t
CSS
S Active Setup Time (relative to C)
10
ns
t
CHSL
S Not Active Hold Time (relative to C)
10
ns
t
DVCH
t
DSU
Data In Setup Time
3
ns
t
CHDX
t
DH
Data In Hold Time
5
ns
t
CHSH
S Active Hold Time (relative to C)
5
ns
t
SHCH
S Not Active Setup Time (relative to C)
5
ns
t
SHSL
t
SHQZ (3)
t
CSH
S Deselect Time
100
ns
t
DIS
Output Disable Time
12
ns
t
CLQV
t
V
Clock Low to Output Valid
12
ns
t
CLQX
t
HO
Output Hold Time
0
ns
t
THSL
Top Sector Lock Setup Time
50
ns
t
SHTL
t
DP (3)
t
RDP (3)
Top Sector Lock Hold Time
100
ns
S to Deep Power-down
3
μ
s
S High to Standby Power mode
30
μ
s
t
PW
(4)
Page Write Cycle Time (256 bytes)
11
25
ms
Page Write Cycle Time (n bytes)
10.2+
n*0.8/256
t
PP
(4)
Page Program Cycle Time (256 bytes)
1.2
5
ms
Page Program Cycle Time (n bytes)
0.4+
n*0.8/256
t
PE
Page Erase Cycle Time
10
20
ms
t
SE
Sector Erase Cycle Time
1
5
s
1.
Details of how to find the date of marking are given in Application Note, AN1995.
2.
t
CH
+ t
CL
must be greater than or equal to 1/ f
C
Value guaranteed by characterization, not 100% tested in production.
3.
4.
When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence
including all the bytes versus several sequences of only a few bytes. (1
n
256)
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