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參數(shù)資料
| 型號(hào)： | M25PE40VMN6G |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | 4 Mbit Uniform Sector, Serial Flash Memory |
| 中文描述： | 4兆位統(tǒng)一部門，串行閃存 |
| 文件頁數(shù)： | 58/60頁 |
| 文件大小： | 315K |
| 代理商： | M25PE40VMN6G |
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Revision history
M25PE40
58/60
14
Revision history
Table 27.
Document revision history
Date
Revision
Changes
01-Apr-2004
0.1
Document written
09-Nov-2004
1.0
Write Protect (W) pin replaced by Top Block Lock (TBL).
Section 2.5: Reset (Reset)
description modified. JEDEC signature
modified. Reset timings t
RLRH
, t
RHSL
and t
SHRH
removed from
Table 19: AC characteristics (33 MHz operation)
and inserted in
Table 21: Reset timings
(t
RHSL
modified). Document status
promoted from Target Specification to Preliminary Data.
01-Dec-2004
2.0
Top Block Lock (TBL) renamed as Top Sector Lock (TSL). Small text
changes. Deep Power-Down mode clarified in
Section 4.6: Active
Power, Standby Power and Deep Power-down modes
.
11-Jan-2005
3.0
Notes removed from
Table 26: Ordering information scheme
.
Wording changes. SO16 package removed, SO8 Wide package
added.
4-Oct-2005
4.0
Added
Table 19: AC characteristics (33 MHz operation)
. Document
status promoted from Preliminary Data to Datasheet.
Table 18: AC
characteristics (25 MHz operation)
updated.
Section 4.2: An easy
way to modify data
,
Section 4.3: A fast way to modify data
,
Section 6.9: Page Write (PW)
and
Section 6.10: Page Program (PP)
updated to explain optimal use of Page Write and Page Program
instructions. Clock slew rate changed from 0.03 to 0.1 V/ns.
Updated
Table 26: Ordering information scheme
. Added Ecopack
information.
11-Aug 2006
5
Changed document to new template; amended figure in Feature
summary; replaced
Figure 4: Bus master and memory devices on
the SPI bus
; amended data in
Table 18
and
Table 19
; amended title
of
Figure 30: VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad
Flat Package No lead 6 × 5 mm, package outline
and added a
footnote; amended name of the MP package in
Table 26: Ordering
information scheme
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M25PE40VMN6P | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25PE40VMN6TG | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25PE40VMN6TP | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25PE40VMP6G | 1A Standard Fixed Output LDO Regulators with Shutdown Switch; Package: TO220FP-5; Constitution materials list: Packing style: Tube packaging; Package quantity: 50; Minimum package quantity: 500; |
| M25PE40VMP6P | 4 Mbit Uniform Sector, Serial Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M25PE40-VMN6G | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:4 Mbit, page-erasable serial Flash memory with byte alterability, 75 MHz SPI bus, standard pinout |
| M25PE40VMN6P | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit, low voltage, Page-Erasable Serial Flash memory with byte alterability, 50 MHz SPI bus, standard pinout |
| M25PE40-VMN6P | 制造商:Micron Technology Inc 功能描述:NOR Flash Serial-SPI 3.3V 4Mbit 512K x 8bit 8ns 8-Pin SOIC N Tray 制造商:Micron Technology Inc 功能描述:FLASH SERL-SPI 3.3V 4MBIT 512KX8 15NS 8SOIC N - Trays 制造商:Micron Technology 功能描述:NOR Flash Serial-SPI 3.3V 4Mbit 512K x 8bit 8ns 8-Pin SOIC N Tray |
| M25PE40VMN6TG | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit, low voltage, Page-Erasable Serial Flash memory with byte alterability, 50 MHz SPI bus, standard pinout |
| M25PE40-VMN6TG | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:4 Mbit, page-erasable serial Flash memory with byte alterability, 75 MHz SPI bus, standard pinout |
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