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| 型號： | M36DR432D |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product |
| 中文描述： | 32兆位的2Mb x16插槽，雙行，頁閃存和4兆位256K x16的SRAM，多個存儲產(chǎn)品 |
| 文件頁數(shù)： | 13/46頁 |
| 文件大?。?/td> | 330K |
| 代理商： | M36DR432D |
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M36DR432C, M36DR432D
– the lock status is cleared for all blocks at power
up; once a block has been locked state can be
cleared only with a reset command. The protec-
tion and lock status can be monitored for each
block using the Autoselect (AS) instruction. Pro-
tected blocks will output a ‘1’ on DQ0 and locked
blocks will output a ‘1’ on DQ1.
Refer to Table 14 for a list of the protection states.
Block Erase (BE) Instruction.
This
uses a minimum of six write cycles. The Erase
Set-up command 80h is written to address 555h
on third cycle after the two Coded cycles. The
Block Erase Confirm command 30h is similarly
written on the sixth cycle after another two Coded
cycles and an address within the block to be
erased is given and latched into the memory.
Additional block Erase Confirm commands and
block addresses can be written subsequently to
erase other blocks in parallel, without further Cod-
ed cycles. All blocks must belong to the same
bank of memory; if a new block belonging to the
other bank is given, the operation is aborted. The
erase will start after an erase timeout period of
100μs. Thus, additional Erase Confirm commands
for other blocks must be given within this delay.
The input of a new Erase Confirm command will
restart the timeout period. The status of the inter-
nal timer can be monitored through the level of
DQ3, if DQ3 is '0' the Block Erase Command has
been given and the timeout is running, if DQ3 is '1',
the timeout has expired and the P/E.C. is erasing
the Block(s). If the second command given is not
an erase confirm or if the Coded cycles are wrong,
the instruction aborts, and the device is reset to
Read Array. It is not necessary to program the
block with 00h as the P/E.C. will do this automati-
cally before erasing to FFh. Read operations with-
in the same bank, after the sixth rising edge of WF
or EF, output the status register bits.
During the execution of the erase by the P/E.C.,
the memory accepts only the Erase Suspend ES
instruction; the Read/Reset RD instruction is ac-
cepted during the 100μs time-out period. Data
Polling bit DQ7 returns '0' while the erasure is in
progress and '1' when it has completed. The Tog-
gle bit DQ6 toggles during the erase operation,
and stops when erase is completed.
After completion the Status Register bit DQ5 re-
turns '1' if there has been an erase failure. In such
a situation, the Toggle bit DQ2 can be used to de-
termine which block is not correctly erased. In the
instruction
case of erase failure, a Read/Reset RD instruction
is necessary in order to reset the P/E.C.
Bank Erase (BKE) Instruction.
This instruction
uses six write cycles and is used to erase all the
blocks belonging to the selected bank. The Erase
Set-up command 80h is written to address 555h
on the third cycle after the two Coded cycles. The
Bank Erase Confirm command 10h is similarly
written on the sixth cycle after another two Coded
cycles at an address within the selected bank. If
the second command given is not an erase con-
firm or if the Coded cycles are wrong, the instruc-
tion aborts and the device is reset to Read Array.
It is not necessary to program the array with 00h
first as the P/E.C. will automatically do this before
erasing it to FFh. Read operations within the same
bank after the sixth rising edge of WF or EF output
the Status Register bits. During the execution of
the erase by the P/E.C., Data Polling bit DQ7 re-
turns '0', then '1' on completion. The Toggle bit
DQ6 toggles during erase operation and stops
when erase is completed. After completion the
Status Register bit DQ5 returns '1' if there has
been an Erase Failure.
Erase Suspend (ES) Instruction.
In a dual bank
memory the Erase Suspend instruction is used to
read data within the bank where erase is in
progress. It is also possible to program data in
blocks not being erased.
The Erase Suspend instruction consists of writing
the command B0h without any specific address.
No Coded Cycles are required. Erase suspend is
accepted only during the Block Erase instruction
execution. The Toggle bit DQ6 stops toggling
when the P/E.C. is suspended within 15μs after
the Erase Suspend (ES) command has been writ-
ten. The device will then automatically be set to
Read Memory Array mode. When erase is sus-
pended, a Read from blocks being erased will out-
put DQ2 toggling and DQ6 at '1'. A Read from a
block not being erased returns valid data. During
suspension the memory will respond only to the
Erase Resume ER and the Program PG instruc-
tions. A Program operation can be initiated during
erase suspend in one of the blocks not being
erased. It will result in DQ6 toggling when the data
is being programmed.
Erase Resume (ER) Instruction.
If
Suspend instruction was previously executed, the
erase operation may be resumed by giving the
command 30h, at an address within the bank be-
ing erased and without any Coded Cycle.
an
Erase
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