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參數(shù)資料
| 型號： | M36DR432D |
| 廠商： | 意法半導體 |
| 英文描述： | 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256K x16 SRAM, Multiple Memory Product |
| 中文描述： | 32兆位的2Mb x16插槽，雙行，頁閃存和4兆位256K x16的SRAM，多個存儲產(chǎn)品 |
| 文件頁數(shù)： | 37/46頁 |
| 文件大?。?/td> | 330K |
| 代理商： | M36DR432D |
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M36DR432C, M36DR432D
Table 32. SRAM Write AC Characteristics
(T
A
= –40 to 85°C; V
DDS
= 1.9V to 2.1V)
Note: 1. t
AS
is measured from the address valid to the beginning of write.
2. t
WR
is measured from the end or write to the address change. t
WR
applied in case a write ends as E1S or WS going high.
3. t
CW
is measured from E1S going low end of write.
4. A Write occurs during the overlap (t
WP
) of low E1S and low WS. A write begins when E1S goes low and WS goes low with asserting
UBS or LBS for single byte operation or simultaneously asserting UBS and LBS for double byte operation. A write ends at the ear-
liest transition when E1S goes high and WS goes high. The t
WP
is measured from the beginning of write to the end of write.
Symbol
Alt
Parameter
SRAM
Unit
Min
Max
t
AVAV
t
WC
Write Cycle Time
85
ns
t
AVE1L
t
AS(1)
Address Valid to Chip Enable 1 Low
0
ns
t
AVE2H
t
AS(1)
Address Valid to Chip Enable 2 High
0
ns
t
AVWH
t
AW
Address Valid to Write Enable High
75
ns
t
AVWL
t
AS(1)
Address Valid to Write Enable Low
0
ns
t
BLWH
t
BW
UBS, LBS Valid to End of Write
75
ns
t
DVE1H
t
DW
Input Valid to Chip Enable 1 High
45
ns
t
DVE2L
t
DW
Input Valid to Chip Enable 2 Low
45
ns
t
DVWH
t
DW
Input Valid to Write Enable High
45
ns
t
E1HAX
t
WR(2)
Chip Enable 1 High to Address Transition
0
ns
t
E1LWH
,
t
E2HWH
t
CW(3)
Chip Select to End of Write
75
ns
t
E2LAX
t
WR(2)
Chip Enable 2 Low to Address Transition
0
ns
t
GHQZ
t
GHZ
Output Enable Higt to Output Hi-Z
25
ns
t
WHAX
t
WR(2)
Write Enable High to Address Transition
0
ns
t
WHDX
t
DH
Write Enable High to Input Transition
0
ns
t
WHQX
t
OW
Write Enable High to Output Transition
5
ns
t
WLQZ
t
WHZ
Write Enable Low to Output Hi-Z
35
ns
t
WLWH
t
WP(4)
Write Enable Pulse Width
65
ns
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