參數(shù)資料
型號: M37735MHBXXXFP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP80
封裝: 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80
文件頁數(shù): 5/93頁
文件大?。?/td> 1802K
代理商: M37735MHBXXXFP
MITSUBISHI MICROCOMPUTERS
M37735MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
10
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
The bus interface unit operates using one of the waveforms (1) to
(10) shown in Figure 5. The standard waveforms are (1) and (2).
The ALE signal is used to latch only the address signal from the
multiplexed signal containing data and address.
The E signal becomes “L” when the bus interface unit reads an
instruction code or data from the memory or when it writes data to
the memory. Whether to perform read or write is controlled by the
R/W signal. The E (except for that in the single-chip mode) and R/W
signals are not directly output to the outside. In the memory expansion
mode or the microprocessor mode, read signal RDE and write signals
WEL
, WEH are output, instead of E and R/W, to the outside of the
chip. During signal E is “L”, signal RDE becomes “L” (in the read cycle)
or signals WEL and WEH become “L” (in the write cycle).
Waveform (1) in Figure 5 is used to access a single byte or two bytes
simultaneously. To read or write two bytes simultaneously, the first
address accessed must be even. Furthermore, when accessing an
external memory area in the memory expansion mode or the
microprocessor mode, set the bus width selection input pin (BYTE)
to “L” (external data bus has a width of 16 bits). The data bus in the
internal memory area is always treated as the 16-bit bus independent
of BYTE.
Fig. 5 Bus access timing
Port P2
E
ALE
Port P2
E
ALE
Internal clock
φ
Internal clock
φ
Port P2
E
ALE
A
D
A
D
A
D A + 1 D
A
D
A + 1
D
A
D
A+1
D
(1)
(2)
(3)
(4)
(5)
(6)
Access time
A
D
A +1
A
D
A
D
A + 1
D
(7)
(8)
(9)
(10)
Access time
D
A
A + 1
D
AD
A + 1
D
Access time
A : Address
D : Data
During signal E is “L” in the memory expansion mode or
the microprocessor mode, signal RDE becomes “L”
(in the read cycle) or signals WEL and WEH become “L”
(in the write cycle).
Port P2
E
ALE
Port P2
E
ALE
Port P2
E
ALE
Port P2
E
ALE
Port P2
E
ALE
Port P2
E
ALE
Port P2
E
ALE
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