參數(shù)資料
型號： M37735MHBXXXFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP80
封裝： 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80
文件頁數(shù)： 7/93頁
文件大?。?/td> 1802K
代理商： M37735MHBXXXFP
12
MITSUBISHI MICROCOMPUTERS
M37735MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
INTERRUPTS
Table 1 shows the interrupt sources and the corresponding interrupt
vector addresses. Reset is also treated as a source of interrupt and
is described in this section.
DBC
is an interrupt used only for debugging.
Interrupts other than reset, DBC, watchdog timer, zero divide, and
BRK instruction all have their respective interrupt control registers.
Table 2 shows the addresses of the interrupt control registers and
Figure 6 shows the bit configuration of the interrupt control register.
The interrupt request bit is automatically cleared by hardware during
reset or when processing an interrupt. Also, interrupt request bits
other than DBC and watchdog timer can be cleared by software.
INT0
to INT2 are external interrupts, and whether to cause an interrupt
at the input level (level sense) or at the edge (edge sense) can be
selected with the level sense/edge sense selection bit. Furthermore,
the polarity of the interrupt input can be selected with a polarity
selection bit.
In the INT2 /Key input interrupt, whether to input an interrupt request
from the INT2 pin or the KI0 – KI3 pins can be selected by bit 7 of the
port function control register (refer to Figure 11).
Timer and UART interrupts are described in the respective section.
The priority of interrupts when multiple interrupts are caused
simultaneously is partially fixed by hardware, but it can also be
adjusted by software as shown in Figure 7. The hardware priority is
fixed as follows:
reset > DBC > watchdog timer > other interrupts
Table 1. Interrupt sources and the interrupt vector addresses
Fig. 6 Interrupt control register bit configuration
7
Interrupt priority level selection bits
6 5 4 3 2 1 0
Interrupt request bit
0 : No interrupt
1 : Interrupt
Interrupt control register configuration for timers A0 to A4, timers B0 to B2, UART0, UART1 and
A-D/UART2 trans./rece.
7
Interrupt priority level selection bits
6 5 4 3 2 1 0
Interrupt request bit
0 : No interrupt
1 : Interrupt
Polarity selection bit
0 : Interrupt request bit is set at “H” level for level sense or at the falling
edge for edge sence.
1 : Interrupt request bit is set at “L” level for level sense or at the rising
edge for edge sense.
Level sense/edge sense selection bit
0 : Edge sense
1 : Level sense
Interrupt control register configuration for INT0 to INT2/Key input.
Interrupts
Vector addresses
A-D/UART2 trans./rece.
00FFD616
00FFD716
UART1 transmit
00FFD816
00FFD916
UART1 receive
00FFDA16
00FFDB16
UART0 transmit
00FFDC16
00FFDD16
UART0 receive
00FFDE16
00FFDF16
Timer B2
00FFE016
00FFE116
Timer B1
00FFE216
00FFE316
Timer B0
00FFE416
00FFE516
Timer A4
00FFE616
00FFE716
Timer A3
00FFE816
00FFE916
Timer A2
00FFEA16
00FFEB16
Timer A1
00FFEC16
00FFED16
Timer A0
00FFEE16
00FFEF16
INT2
/Key input
00FFF016
00FFF116
INT1
00FFF216
00FFF316
INT0
00FFF416
00FFF516
Watchdog timer
00FFF616
00FFF716
DBC
(unusable)
00FFF816
00FFF916
BRK instruction
00FFFA16
00FFFB16
Zero divide
00FFFC16
00FFFD16
Reset
00FFFE16
00FFFF16
相關(guān)PDF資料
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