參數(shù)資料
型號: M37735MHBXXXFP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP80
封裝: 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80
文件頁數(shù): 62/93頁
文件大?。?/td> 1802K
代理商: M37735MHBXXXFP
62
MITSUBISHI MICROCOMPUTERS
M37735MHBXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
The wait/stop state is terminated by interrupt acceptance or reset.
Accordingly, it is necessary to prepare the state in which any interrupt
can be accepted before the WIT/STP instruction is executed.
Additionally, it is necessary to set the system clock stop bit at wait
state before the WIT instruction is executed.
When the WIT/STP instruction is executed in a bus access cycle,
the bus enters the non-access state (each signal of E, RDE, WEL and
WEH
is at “H”) because internal clock
φ (or oscillation) is stopped
after the read/write in this cycle is finished. Pins P00/CS0 to P33/HLDA
normally retain the state at which internal clock
φ is stopped in the
wait/stop state.
However, only in the memory expansion mode and the microprocessor
mode, arbitrary data which is set in the port P0 to P3 latches can be
output from pins P00/CS0 to P33/HLDA even at the wait/stop state
when the following conditions are satisfied before the WIT/STP
instruction execution.
The standby state selection bit (bit 0 of the port function control
register) is set to “1”.
“FF16” is set into the port P0 to P3 direction registers.
Furthermore, when the standby state selection bit is set to “1” and bit
6 of the oscillation circuit control register 0 (signal output disable
selection bit) is set to “1”, “L” level can be output from the E/RDE pin
at the wait/stop state. For the signal output disable selection bit, refer
to Table 8 on the processor mode section.
Note that the function of arbitrary data output cannot be emulated
using a debugger.
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