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參數(shù)資料
| 型號： | M58WR064HU70ZB6U |
| 元件分類： | PROM |
| 英文描述： | 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA44 |
| 封裝： | 7.70 X 9 MM, 0.50 MM PITCH, ROHS COMPLIANT, VFBGA-44 |
| 文件頁數(shù)： | 26/117頁 |
| 文件大?。?/td> | 2300K |
| 代理商： | M58WR064HU70ZB6U |
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Signal descriptions
M58WR064HU M58WR064HL
16/117
2.7
Reset/Power-Down (RP)
The Reset/Power-Down input provides a hardware reset of the memory, and/or power-down
functions, depending on the settings in the Configuration Register. When Reset/Power-
Down is at VIL, the memory is in reset mode: the outputs are high impedance and the
current consumption is reduced to the Standby Supply Current IDD3, or to the Reset/Power-
Locked state and the bits of the Configuration Register are reset except for Power-Down bit
CR5. When Reset/Power-Down is at VIH, the device is in normal operation. Exiting reset
mode the device enters Asynchronous Read mode, but a negative transition of Chip Enable
or Latch Enable is required to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied
2.8
Latch Enable (L)
Latch Enable latches the ADQ0-ADQ15 and A16-A21 address bits on its rising edge. The
address latch is transparent when Latch Enable is at VIL and it is inhibited when Latch
Enable is at VIH.
2.9
Clock (K)
The clock input synchronizes the memory to the microcontroller during synchronous read
operations; the address is latched on a Clock edge (rising or falling, according to the
configuration settings) when Latch Enable is at VIL. Clock is don't care during asynchronous
read and in write operations.
2.10
Wait (WAIT)
Wait is an output signal used during synchronous read to indicate whether the data on the
output bus are valid. This output is high impedance when Chip Enable is at VIH or Reset is
at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance.
The WAIT signal is forced deasserted when Output Enable is at VIH.
2.11
Bus Invert (BINV)
Bus invert is an input/output signal used to reduce the amount of power required to switch
the external address/data bus. Power is saved by inverting the data on ADQ0-ADQ15 each
time the inversion results in a reduced number of pin transitions. Data is inverted when BINV
is at VIH (i.e. if the data is AAAAh and BINV is at VIH, AAAAh becomes 5555h). BINV is high
impedance when Chip Enable or Output Enable is at VIH or when Reset/Power Down is at
VIL.
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| M59DR032F100N1T | 2M X 16 FLASH 1.8V PROM, 100 ns, PDSO48 |
| M5F7924 | 24 V FIXED NEGATIVE REGULATOR, PSFM3 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M58WR064KB70ZB6E | 制造商:Micron Technology Inc 功能描述:WIRELESS FLASH VFBGA 7.7X9.0X1.0 56 8X7 0.75 - Trays 制造商:Micron Technology Inc 功能描述:IC FLASH 64MBIT 70NS 56VFBGA |
| M58WR064KB70ZB6F | 制造商:Micron Technology Inc 功能描述:FLASH 28F640W18TD 60 VF-PBGA56 SB48 EX - Tape and Reel |
| M58WR064KB70ZB6F TR | 制造商:Micron Technology Inc 功能描述:IC FLASH 64MBIT 70NS 56VFBGA |
| M58WR064KB7AZB6E | 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays 制造商:Micron Technology Inc 功能描述:IC FLASH 64MBIT 70NS 56VFBGA |
| M58WR064KB7AZB6F | 制造商:Micron Technology Inc 功能描述:WIRELESS - Tape and Reel |
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