參數(shù)資料
型號(hào): M58WR064HU70ZB6U
元件分類: PROM
英文描述: 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA44
封裝: 7.70 X 9 MM, 0.50 MM PITCH, ROHS COMPLIANT, VFBGA-44
文件頁數(shù): 62/117頁
文件大?。?/td> 2300K
代理商: M58WR064HU70ZB6U
M58WR064HU M58WR064HL
Read modes
49/117
9
Read modes
Read operations can be performed in two different ways depending on the settings in the
Configuration Register. If the clock signal is ‘don’t care’ for the data output, the read
operation is Asynchronous; if the data output is synchronized with clock, the read operation
is Synchronous.
The Read mode and data output format are determined by the Configuration Register. (See
Section 8: Configuration Register for details). All banks supports both asynchronous and
synchronous read operations. The Multiple Bank architecture allows read operations in one
bank, while write operations are being executed in another (see Tables 12 and 13).
9.1
Asynchronous Read mode
In Asynchronous Read operations the clock signal is ‘don’t care’. The device outputs the
data corresponding to the address latched, that is the memory array, Status Register,
Common Flash Interface or Electronic Signature depending on the command issued. CR15
in the Configuration Register must be set to ‘1’ for Asynchronous operations.
In Asynchronous Read mode, the WAIT signal is always deasserted.
The device features an Automatic Standby mode. During asynchronous read operations,
after a bus inactivity of 150ns, the device automatically switches to the Automatic Standby
mode. In this condition the power consumption is reduced to the standby value IDD4 and the
outputs are still driven.
相關(guān)PDF資料
PDF描述
M59DR032F100N1T 2M X 16 FLASH 1.8V PROM, 100 ns, PDSO48
M5F7924 24 V FIXED NEGATIVE REGULATOR, PSFM3
M5F7920 20 V FIXED NEGATIVE REGULATOR, PSFM3
M5F7918 18 V FIXED NEGATIVE REGULATOR, PSFM3
M5F7915 15 V FIXED NEGATIVE REGULATOR, PSFM3
相關(guān)代理商/技術(shù)參數(shù)
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