參數(shù)資料
型號： M58WR064HU70ZB6U
元件分類： PROM
英文描述： 4M X 16 FLASH 1.8V PROM, 70 ns, PBGA44
封裝： 7.70 X 9 MM, 0.50 MM PITCH, ROHS COMPLIANT, VFBGA-44
文件頁數(shù)： 64/117頁
文件大?。?/td> 2300K
代理商： M58WR064HU70ZB6U
Read modes
M58WR064HU M58WR064HL
9.2
Synchronous Burst Read mode
In Synchronous Burst Read mode the data is output in bursts synchronized with the clock. It
is possible to perform burst reads across bank boundaries.
Synchronous Burst Read mode can only be used to read the memory array. For other read
operations, such as Read Status Register, Read CFI and Read Electronic Signature, Single
Synchronous Read or Asynchronous Random Access Read must be used.
In Synchronous Burst Read mode the flow of the data output depends on parameters that
are configured in the Configuration Register.
A burst sequence is started at the first clock edge (rising or falling depending on Valid Clock
Edge bit CR6 in the Configuration Register) after the falling edge of Latch Enable.
Addresses are internally incremented and after a delay of 2 to 5 clock cycles (X latency bits
CR13-CR11) the corresponding data are output on each clock cycle.
The number of Words to be output during a Synchronous Burst Read operation can be
configured as 4, 8 or 16 Words or Continuous (Burst Length bits CR2-CR0). The data can
be configured to remain valid for one or two clock cycles (Data Output Configuration bit
CR9).
The order of the data output can be modified through the Burst Type and the Wrap Burst bits
in the Configuration Register. The burst sequence may be configured to be sequential or
interleaved (CR7). The burst reads can be confined inside the 4, 8 or 16 Word boundary
(Wrap) or overcome the boundary (No Wrap). If the starting address is aligned to the Burst
Length (4, 8 or 16 Words), the wrapped configuration has no impact on the output
sequence. Interleaved mode is not allowed in Continuous Burst Read mode or with No
Wrap sequences.
A WAIT signal may be asserted to indicate to the system that an output delay will occur. This
delay will depend on the starting address of the burst sequence; the worst case delay will
occur when the sequence is crossing a 16 word boundary and the starting address was at
the end of a four word boundary.
WAIT is asserted during X-latency, the Wait state and at the end of a 4, 8 and 16 Word
burst. It is only deasserted when output data are valid or when G is at VIH. In Continuous
Burst Read mode a Wait state will occur when crossing the first 16 Word boundary. If the
burst starting address is aligned to a 4 Word Page, the Wait state will not occur.
The WAIT signal can be configured to be active Low or active High by setting CR10 in the
Configuration Register.
AC waveforms, for details.
相關(guān)PDF資料
PDF描述
M59DR032F100N1T 2M X 16 FLASH 1.8V PROM, 100 ns, PDSO48
M5F7924 24 V FIXED NEGATIVE REGULATOR, PSFM3
M5F7920 20 V FIXED NEGATIVE REGULATOR, PSFM3
M5F7918 18 V FIXED NEGATIVE REGULATOR, PSFM3
M5F7915 15 V FIXED NEGATIVE REGULATOR, PSFM3
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M58WR064KB70ZB6E 制造商:Micron Technology Inc 功能描述:WIRELESS FLASH VFBGA 7.7X9.0X1.0 56 8X7 0.75 - Trays 制造商:Micron Technology Inc 功能描述:IC FLASH 64MBIT 70NS 56VFBGA
M58WR064KB70ZB6F 制造商:Micron Technology Inc 功能描述:FLASH 28F640W18TD 60 VF-PBGA56 SB48 EX - Tape and Reel
M58WR064KB70ZB6F TR 制造商:Micron Technology Inc 功能描述:IC FLASH 64MBIT 70NS 56VFBGA
M58WR064KB7AZB6E 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays 制造商:Micron Technology Inc 功能描述:IC FLASH 64MBIT 70NS 56VFBGA
M58WR064KB7AZB6F 制造商:Micron Technology Inc 功能描述:WIRELESS - Tape and Reel
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