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參數(shù)資料
| 型號： | M66287FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 262144-word x 8-bit x 3-FIELD MEMORY |
| 中文描述： | 262144字× 8位× 3場記憶 |
| 文件頁數(shù)： | 5/21頁 |
| 文件大?。?/td> | 196K |
| 代理商： | M66287FP |
MITSUBISHI <DIGITAL ASSP>
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
2002 MITSUBISHI ELECTRIC CORPORATION
5
MODE SET
MODE<3:1> should be set to “L” or “H” as shown below according to the five modes to be used.
MODE 3
MODE 2
MODE 1
Operation mode
L
L
L
MODE 1
L
L
H
MODE 2
L
H
L
MODE 3
L
H
H
MODE 4
H
L
L
MODE 5
other than those above
MODE 1
MODE 1 OPERATION DESCRIPTIONS
<Mode 1>
In mode 1, three FIFO memories with 8-bit data bus can be controlled completely
individually. Taking FIFO (A) as an example, the operation of FIFO memory is
described below. The operation of FIFO (B) and FIFO (C) are the same as that of
FIFO (A).
When write enable input WEA is "L", the contents of data input DA<7:0> are
written into FIFO (A) in synchronization with the rising of write clock input WCKA.
At this time, the write address counter of FIFO (A) is incremented.
When WEA is "H", writing into FIFO (A) is disabled and the write address counter
of FIFO (A) is stopped.
When write reset input WRESA is "L", the write address counter of FIFO (A) is
initialized.
When read enable input REA is "L", the contents of FIFO (A) are outputted to data output QA<7:0> in synchronization with
the rising of read clock input RCKA. At this time, the read address counter of FIFO (A) is incremented.
When REA is "H", reading from FIFO (A) is disabled and the read address counter of FIFO (A) is stopped. Also QA<7:0>
become high impedance state.
When read reset input RRESA is "L", the read address counter of FIFO (A) is initialized.
Note : The three pieces of 256K-word x 8-bit FIFO can be operated completely independently.
DA<7:0>
WCKA
WRESA
WEA
8
8
256K
x
8-bit
FIFO(A)
QA<7:0>
RCKA
RRESA
REA
DB<7:0>
WCKB
WRESB
WEB
QB<7:0>
RCKB
RRESB
REB
8
8
256K
x
8-bit
FIFO(B)
DC<7:0>
WCKC
WRESC
WEC
QC<7:0>
RCKC
RRESC
REC
8
8
256K
x
8-bit
FIFO(C)
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