參數(shù)資料
型號(hào)： M66287FP
廠商： Mitsubishi Electric Corporation
英文描述： 262144-word x 8-bit x 3-FIELD MEMORY
中文描述： 262144字× 8位× 3場(chǎng)記憶
文件頁(yè)數(shù)： 8/21頁(yè)
文件大小： 196K
代理商： M66287FP
MITSUBISHI <DIGITAL ASSP>
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
2002 MITSUBISHI ELECTRIC CORPORATION
8
MODE 4 OPERATION DESCRIPTIONS
<Mode 4>
In mode 4, two FIFO memories with 12-bit data bus can be controlled completely
individually. Taking FIFO (A) as an example, the operation of FIFO memory is
described below. The operation of FIFO (B) is the same as that of FIFO (A).
When write enable input WEA is "L", the contents of data input DA<7:0> and
DB<3:0>are written into FIFO (A) in synchronization with the rising of write clock
input WCKA. At this time, the write address counter of FIFO (A) is incremented.
When WEA is "H", writing into FIFO (A) is disabled and the write address counter
of FIFO (A) is stopped.
When write reset input WRESA is "L", the write address counter of FIFO (A) is
initialized.
When read enable input REA is "L", the contents of FIFO (A) are outputted to data output QA<7:0> and QB<3:0> in
synchronization with the rising of read clock input RCKA. At this time, the read address counter of FIFO (A) is incremented.
When REA is "H", reading from FIFO (A) is disabled and the read address counter of FIFO (A) is stopped. Also QA<7:0>
and QB<3:0> become high impedance state.
When read reset input RRESA is "L", the read address counter of FIFO (A) is initialized.
Also, set the 12-bit I/O buses of FIFO (A) and FIFO (B) as shown in the table below.
In mode 4, all pins for the A-system and B-system, DC<7:0> and QC<7:0> are only used. Therefore the write/read control
pins for the C-system should be fixed at "L" or "H".
External pin
name
Data
bus of FIFO
(A)
11-bit
10-bit
9-bit
8-bit
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
input
External pin
name
Data output
bus of FIFO
(A)
11-bit
10-bit
9-bit
8-bit
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
External pin
name
Data
bus of FIFO
(B)
11-bit
10-bit
9-bit
8-bit
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
input
External pin
name
Data output
bus of FIFO
(B)
11-bit
10-bit
9-bit
8-bit
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
DA<7>
DA<6>
DA<5>
DA<4>
DA<3>
DA<2>
DA<1>
DA<0>
DB<3>
DB<2>
DB<1>
DB<0>
QA<7>
QA<6>
QA<5>
QA<4>
QA<3>
QA<2>
QA<1>
QA<0>
QB<3>
QB<2>
QB<1>
QB<0>
DC<7>
DC<6>
DC<5>
DC<4>
DC<3>
DC<2>
DC<1>
DC<0>
DB<7>
DB<6>
DB<5>
DB<4>
QC<7>
QC<6>
QC<5>
QC<4>
QC<3>
QC<2>
QC<1>
QC<0>
QB<7>
QB<6>
QB<5>
QB<4>
Note : The two pieces of 256K-word x 12-bit FIFO can be operated completely independently.
DA<7:0>
DB<3:0>
WCKA
WRESA
WEA
12
12
256K
x
12-bit
FIFO(A)
QA<7:0>
QB<3:0>
256K
x
12-bit
FIFO(B)
12
12
QC<7:0>
QB<7:4>
DB<7:4>
WCKB
WRESB
WEB
DC<7:0>
RCKB
RRESB
REB
RCKA
RRESA
REA
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