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參數(shù)資料
| 型號： | M66287FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 262144-word x 8-bit x 3-FIELD MEMORY |
| 中文描述： | 262144字× 8位× 3場記憶 |
| 文件頁數(shù)： | 9/21頁 |
| 文件大?。?/td> | 196K |
| 代理商： | M66287FP |
MITSUBISHI <DIGITAL ASSP>
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
2002 MITSUBISHI ELECTRIC CORPORATION
9
MODE 5 OPERATION DESCRIPTIONS
<Mode 5>
In mode 5, two FIFO memories with 12-bit data bus are cascade-connected
and it is possible to generate delay data for 2-lines without external wiring.
When write enable input WEA is "L", the contents of data input DA<7:0> and
DB<3:0> are written into FIFO (A) in synchronization with the rising of write
clock input WCKA. At this time, the write address counter of FIFO (A) is
incremented.
When WEA is "H", writing into FIFO (A) is disabled and the write address
counter of FIFO (A) is stopped.
When write reset input WRESA is "L", the write address counter of FIFO (A) is
initialized.
When read enable input REA is "L", the contents of FIFO (A) and FIFO (B) are outputted to each QA<7:0>, QB<3:0> and
QC<7:0> and QB<7:4> in synchronization with the rising of read clock input RCKA. At this time, the read address counters
of FIFO (A) and FIFO (B) are incremented.
Also the data of FIFO (A) is written into FIFO (B) in synchronization with the rising of RCKA. At this time, the write address
counter of FIFO (B) is incremented simultaneously.
When REA is "H", reading from FIFO (A) and FIFO (B) is disabled and the read address counter of each FIFO is stopped.
Also all data outputs become high impedance state. And writing into FIFO (B) is disabled and the write address counter of
FIFO (B) is stopped.
When read reset input RRESA is "L", the read address counter of FIFO (A) and the write address counter/read address
counter of FIFO (B) are initialized.
Also, set the 12-bit I/O buses of FIFO (A) and FIFO (B) as shown in the table below.
In mode 5, all pins for the A-system, DB<3:0>, QB<7:0> and QC<7:0> are only used. Therefore the write/read control pins
for the B-system and the C-system, DB<7:4> and DC<7:0> should be fixed at "L" or "H".
External pin
name
Data
bus of FIFO
(A)
11-bit
10-bit
9-bit
8-bit
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
input
External pin
name
Data output
bus of FIFO
(A)
11-bit
10-bit
9-bit
8-bit
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
External pin
name
Data output
bus of FIFO
(B)
11-bit
10-bit
9-bit
8-bit
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
DA<7>
DA<6>
DA<5>
DA<4>
DA<3>
DA<2>
DA<1>
DA<0>
DB<3>
DB<2>
DB<1>
DB<0>
QA<7>
QA<6>
QA<5>
QA<4>
QA<3>
QA<2>
QA<1>
QA<0>
QB<3>
QB<2>
QB<1>
QB<0>
QC<7>
QC<6>
QC<5>
QC<4>
QC<3>
QC<2>
QC<1>
QC<0>
QB<7>
QB<6>
QB<5>
QB<4>
Note : The two pieces of 256K-word x 12-bit FIFO are cascade-connected, and a line delay data can be made easily.
Write and read operation of FIFO at the 2nd line is controlled by the read system pin of the 1st line.
DA<7:0>
DB<3:0>
WCKA
WRESA
WEA
12
12
256K
x
12-bit
FIFO(A)
QA<7:0>
QB<3:0>
256K
x
12-bit
FIFO(B)
12
12
QC<7:0>
QB<7:4>
RCKA
RRESA
REA
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