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參數資料
| 型號： | M66287FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 262144-word x 8-bit x 3-FIELD MEMORY |
| 中文描述： | 262144字× 8位× 3場記憶 |
| 文件頁數： | 6/21頁 |
| 文件大?。?/td> | 196K |
| 代理商： | M66287FP |
MITSUBISHI <DIGITAL ASSP>
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
2002 MITSUBISHI ELECTRIC CORPORATION
6
MODE 2 OPERATION DESCRIPTIONS
<Mode 2>
In mode 2, three FIFO memories with 8-bit data bus are cascade-connected
and it is possible to generate delay data for 3-lines without external wiring.
When write enable input WEA is "L", the contents of data input DA<7:0> are
written into FIFO (A) in synchronization with the rising of write clock input
WCKA. At this time, the write address counter of FIFO (A) is incremented.
When WEA is "H", writing into FIFO (A) is disabled and the write address
counter of FIFO (A) is stopped.
When write reset input WRESA is "L", the write address counter of FIFO (A) is
initialized.
When read enable input REA is "L", the contents of FIFO (A), FIFO (B) and
FIFO (C) are outputted to each QA<7:0>, QB<7:0>, QC<7:0> in
synchronization with the rising of read clock input RCKA. At this time, the read
address counters of all FIFOs are incremented.
Also the data of the upper FIFO is written into the lower FIFO in synchronization with the rising of RCKA. At this time, the
write address counters of FIFO (B) and FIFO (C) are incremented simultaneously.
When REA is "H", reading from FIFO (A), FIFO (B) and FIFO (C) is disabled and the read address counter of each FIFO is
stopped. Also all data outputs become high impedance state. And writing into FIFO (B) and FIFO (C) is disabled and the
write address counters of FIFO (B) and FIFO (C) are stopped.
When read reset input RRESA is "L", the read address counter of FIFO (A) and the write address counters/read address
counters of FIFO (B) and FIFO (C) are initialized.
And, in mode 2, all pins for the A-system, QB<7:0> and QC<7:0> are only used. Therefore the write/read control pins for
the B-system and C-sytsem, DB<7:0> and DC<7:0> should be fixed at "L" or "H".
Note : The three pieces of 256K-word x 8-bit FIFO are cascade-connected, and a line delay data can be made
easily. Write and read operation of FIFO after the 2nd line is controlled by the read system pin of the 1st
line.
DA<7:0>
WCKA
WRESA
WEA
8
8
256K
x
8-bit
FIFO(A)
QA<7:0>
RCKA
RRESA
REA
QB<7:0>
8
256K
x
8-bit
FIFO(B)
8
QC<7:0>
8
256K
x
8-bit
FIFO(C)
8
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