- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄69017 > M66596FP UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 PDF資料下載
參數(shù)資料
| 型號(hào)： | M66596FP |
| 元件分類(lèi)： | 總線(xiàn)控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 0.50 MM PITCH, LQFP-64 |
| 文件頁(yè)數(shù)： | 128/131頁(yè) |
| 文件大?。?/td> | 1595K |
| 代理商： | M66596FP |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)當(dāng)前第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)
M66596FP/WG
rev .1.00
2006.3.14
page 96 of 127
3.9.5
Isochronous transfer transmission buffer flush
In the Peripheral mode if a (u) SOF packet is received without an IN token having been received in the interval
frame during isochronous data transmission, the controller operates as a IN token had been corrupted, and clears
the buffer for which transmission is enabled, putting that buffer in the writing enabled state.
If a double buffer is being used at that time and writing has been finished to both buffers, the buffer memory that
was cleared is seen as the data having been sent at the same interval frame, and transmission is enabled for the
other buffer memory.
The timing at which the operation of the buffer flush function begins varies depending on the value set for the
IITV bit.
(1)
If IITV=0
The buffer flush operation starts from the next frame after the pipe becomes valid.
(2)
In any case other than IITV=0
The buffer flush operation is carried out subsequent to the first normal transaction.
Figure 3.27 shows an example of the buffer flush function of the controller. When an unanticipated token prior to
the interval frame is received, the controller sends the written data or a Zero-Length packet are sent in accordance
with buffer state.
Transmission enabled state
Writing in
progress
Buffer A
Buffer B
Writing completed
Empty state
Writing in
progress
Writing completed
Writing in
progress
Writing completed
Transmission enabled state
Figure 3.27 Example of buffer flush function operation
Figure 3.28 shows an example of the controller generating an interval error. There are five types of interval errors,
as noted below. The interval error is generated at the timing indicated by
in the illustration, and the buffer flush
function is activated.
If the interval error occurs during an IN transfer, the buffer flush function is activated, and if it occurs during an
OUT transfer an NRDY interrupt is generated.
The OVRN bit should be used to distinguish between NRDY interrupts such as received packet errors and overrun
errors.
In response to tokens that are shaded in the illustration, responses occur based on the buffer memory status.
(1)
IN direction
(a) If the buffer is in the transmission enabled state, the data is transferred as a normal response .
(b) If the buffer is in the transmission disabled state, a Zero-Length packet is sent and an underrun error
occurs.
(2)
OUT direction
(a) If the buffer is in the reception enabled state, the data is received as a normal response.
(b) If the buffer is in the reception disabled state, the data is decarded and an overrun error occurs.
Token
Normal transfer
Token
Token damaged
Token
Token delayed
Token
Frame misaligned
Token
Packet inserted
Token
1
SOF
Frame misaligned
Figure 3.28 Example of interval error being generated when “IITV=1”
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M68HC11D3CFB1 | 8-BIT, MROM, 1 MHz, MICROCONTROLLER, PQFP44 |
| M68HC711D0CFN | 8-BIT, 2 MHz, MICROCONTROLLER, PQCC44 |
| M68HC711D0CFB | 8-BIT, 2 MHz, MICROCONTROLLER, PQFP44 |
| M68HC711D3CFB1 | 8-BIT, MROM, 1 MHz, MICROCONTROLLER, PQFP44 |
| M68HC711D3CP1 | 8-BIT, MROM, 1 MHz, MICROCONTROLLER, PDIP40 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M66596FP#RB0Z | 制造商:Renesas Electronics Corporation 功能描述:MCU - Trays 制造商:Renesas Electronics 功能描述:USB Device Controller 64-Pin LQFP Cut Tape 制造商:Renesas Electronics 功能描述:USB Device Controller 64-Pin LQFP Tray 制造商:Renesas 功能描述:USB Device Controller 64-Pin LQFP |
| M66596FPRB0Z | 制造商:Renesas Electronics Corporation 功能描述:USB2.0 Dual Function Controller,LQFP64 |
| M66596WG | 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:ASSP (USB2.0 Dual Function Controller) |
| M66596WG#RB0Z | 制造商:Renesas Electronics 功能描述:Tray 制造商:Renesas 功能描述:0 |
| M6668 | 制造商:Tamura Corporation of America 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。