參數(shù)資料
型號(hào): M66596FP
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 0.50 MM PITCH, LQFP-64
文件頁數(shù): 90/131頁
文件大?。?/td> 1595K
代理商: M66596FP
M66596FP/WG
rev .1.00
2006.3.14
page 61 of 127
DTCH
Full-Speed detach
detect
When Host mode, interruption can be generated when
peripheral device is detached at the time of Full-Speed
mode. Please perform detach detection by S/W, such as
detecting ignore packet from peripheral device at the
time of Hi-Speed mode.
Host
-
Table 3.8 shows the INT_N pin operations of the controller. If multiple interrupt causes have occurred, the method
used for INT_N pin output can be set using the INTL bit of the INTENB1
register. The operation setting for the
INT_N pin should be set to match the user system.
Table 3.8 INT_N pin operations
INT_N pin
operation
INTL setting
When one interrupt cause occurred
When multiple interrupt causes occurred
Edge sensing
(“INTL=0”)
“L” level output until the cause has been
eliminated
When one cause is eliminated, the 32 clock tim
e is negated (“H” pulse output) at 48 MHz.
Level sensing
(“INTL=1”)
“L” level output until the cause has been
eliminated
“L” level is output until all of the causes have
been eliminated.
Interrupt cause 1
Interrupt cause 2
INT_N pin
<Edge sensing>
Cause 1 occurs
Cause 2 occurs
Cause 1 cleared
Cause 2 cleared
Negated interval
Interrupt cause 1
Interrupt cause 2
INT_N pin
<Level sensing>
Cause 1 occurs
Cause 2 occurs
Cause 1 cleared
Cause 2 cleared
Figure 3.11 INT_N pin operation
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