- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄69017 > M66596FP UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 PDF資料下載
參數(shù)資料
| 型號： | M66596FP |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 0.50 MM PITCH, LQFP-64 |
| 文件頁數(shù)： | 52/131頁 |
| 文件大?。?/td> | 1595K |
| 代理商： | M66596FP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁當前第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁
M66596FP/WG
rev .1.00
2006.3.14
page 27 of 127
CFIFO port selection register [CFIFOSEL]
<Address: 1EH>
D0FIFO port selection register [D0FIFOSEL]
<Address: 24H>
D1FIFO port selection register [D1FIFOSEL]
<Address: 2AH>
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RCNT
REW
DCLRM DREQE
MBW
TRENB TRCLR DEZPM
ISEL
CURPIPE
0
-
0
-
0
-
0
-
0
?
0
-
0
-
0
-
0
-
0
?
0
-
0
?
0
-
0
-
0
-
0
Bit
Name
Function
S/W
H/W
Note
15 RCNT
Read Count mode
0: The DTLN bit is cleared when all of the
reception data has been read.
1: The DTLN bit is decremented when the
reception data is read.
R/W
R
14 REW
Buffer pointer rewind
0:
Invalid.
1: The buffer pointer is rewound.
R(0)/W R/W(0) 3.4.2.2
13 DCLRM
This is the Auto Buffer Memory clear
mode accessed after the data for the
specified pipe has been read.
0: The Auto Buffer Clear mode is disabled.
1: The Auto Buffer Clear mode is enabled.
R/W
R
12 DREQE
DREQ signal output enabled
0: Output is disabled.
1: Output is enabled.
R/W
R
11 Nothing is placed here. This should be fixed at “0”.
10 MBW
FIFO port access bit width
0: 8-bit width
1: 16-bit width
R/W
R
9
TRENB
Transaction counter enabled
0: The transaction counter function is invalid.
1: The transaction counter function is valid.
R/W
R
8
TRCLR
Transaction counter clear
0: Invalid
1: The current count is cleared.
R(0)/
W(1)
R
7
DEZPM
Zero-Length Packet Added mode
0: No packet is added.
1: The packet is added.
R/W
R
6
Nothing is placed here. This should be fixed at “0”.
5
ISEL
Access direction of the FIFO port when
DCP is selected
0: This selects reading from the buffer
memory.
1: This selects writing to the buffer memory.
R/W
R
4-3 Nothing is placed here. These should be fixed at “0”.
2-0 CURPIPE
FIFO port access pipe specification
000: DCP / No specification
001: Pipe 1
010: Pipe 2
011: Pipe 3
100: Pipe 4
101: Pipe 5
110: Pipe 6
111: Pipe 7
R/W
R
<<Notes>>
*2) The DCLRM, DREQE, TRENB, TRCLR and DEZPM bits are valid for the D0/D1FIFOSEL registers. The
DCLRM
, TRENB and TRCLR bits are valid when the receiving direction (reading from the buffer memory) has been
set for the pipe specified by the CURPIPE bit. The DEZPM bit is valid when the sending direction (writing to the
buffer memory) has been set for the pipe specified by the CURPIPE bit.
*3) The ISEL bit is valid only when DCP is selected using the CFIFO port selection register. Software should set the
ISEL
bit according to the folowing (a) or (b).
(a) The setting to CURPIPE bit to DCP (“CURPIPE=”0”) and setting to ISEL bit should be done at the same
time.
(b) First software sets CURPIPE bit to DCP (“CURPIPE=”0”), then it sets ISEL bit after 200ns or more.
*4) Once reading from the buffer memory has begun, the access bit width of the FIFO port cannot be changed until
all of the data has been read. Also, the bit width cannot be changed from the 8-bit width to the 16-bit width
while data is being written to the buffer memory.
*5) Specifying"CURPIPE=0"using the D0/D1FIFOSEL register will be interpreted as no pipe having been specified.
Also, the pipe number should not be changed while DREQ output is enabled.
*6) Don’t set the same pipe to CURPIPE of C/D0 / D1FIFOSEL register.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M68HC11D3CFB1 | 8-BIT, MROM, 1 MHz, MICROCONTROLLER, PQFP44 |
| M68HC711D0CFN | 8-BIT, 2 MHz, MICROCONTROLLER, PQCC44 |
| M68HC711D0CFB | 8-BIT, 2 MHz, MICROCONTROLLER, PQFP44 |
| M68HC711D3CFB1 | 8-BIT, MROM, 1 MHz, MICROCONTROLLER, PQFP44 |
| M68HC711D3CP1 | 8-BIT, MROM, 1 MHz, MICROCONTROLLER, PDIP40 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M66596FP#RB0Z | 制造商:Renesas Electronics Corporation 功能描述:MCU - Trays 制造商:Renesas Electronics 功能描述:USB Device Controller 64-Pin LQFP Cut Tape 制造商:Renesas Electronics 功能描述:USB Device Controller 64-Pin LQFP Tray 制造商:Renesas 功能描述:USB Device Controller 64-Pin LQFP |
| M66596FPRB0Z | 制造商:Renesas Electronics Corporation 功能描述:USB2.0 Dual Function Controller,LQFP64 |
| M66596WG | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:ASSP (USB2.0 Dual Function Controller) |
| M66596WG#RB0Z | 制造商:Renesas Electronics 功能描述:Tray 制造商:Renesas 功能描述:0 |
| M6668 | 制造商:Tamura Corporation of America 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。