參數(shù)資料
型號： M66596FP
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 0.50 MM PITCH, LQFP-64
文件頁數(shù)： 49/131頁
文件大?。?/td> 1595K
代理商： M66596FP
M66596FP/WG
rev .1.00
2006.3.14
page 24 of 127
The DMA0CFG register controls the input/output pins used for the DMA0 interface and the D0FIFO port, and the
DMA1CFG
register controls the input/output pins used for the DMA1 interface and the D1FIFO port.
DMA0 pin configuration register [DMA0CFG]
<Address: 0CH>
DMA1 pin configuration register [DMA1CFG]
<Address: 0EH>
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DREQA BURST
DACKA
DFORM
DENDA PKTM DENDE
OBUS
?
0
-
0
-
0
?
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
?
0
-
0
?
Bit
Name
Function
S/W
H/W
Note
15 Nothing is placed here. This should be fixed at “0”.
14 DREQA
DREQx_N signal polarity selection
This specifies the active state for the DREQx_N
pin.
0: Low active
1: High active
R/W
R
-
13 BURST
Burst mode
0: Cycle steal transfer
1: Burst transfer
R/W
R
12-11 Nothing is placed here. These should be fixed at “0”.
10 DACKA
DACKx_N signal polarity selection
This specifies the active state for the DACKx_N
pin.
0: Low active
1: High active
R/W
R
-
9-7 DFORM
DMA transfer signal selection
011:
Only the DACKx_N signal is used (CPU
bus).
000:
The Address signal + the RD_N/WRx_
signals are used (CPU bus).
010:
The DACKx_N + the RD_N/WRx_N
signals are used (CPU bus).
100:
The DACKx_N signal is used (split bus).
110:
The DACK0_N + the DSTB0_N signal
are used (split bus).
001, 101, 111: Reserved
R/W
R
6
DENDA
DEND0_N signal polarity selection
This specifies the active state of the DENDx_N
pin.
0: Low active
1: High active
R/W
R
-
5
PKTM
Packet mode
0: The DENDx_N signal is asserted in transfer
units.
1: The DENDx_N signal is asserted each time
an amount of data corresponding to the buffer
size is transferred.
R/W
R
4
DENDE
DENDx_N signal enabled
0: The DENDx_N signal is disabled
(Hi-Z output).
1: The DENDx_N signal is enabled.
R/W
R
3
Nothing is placed here. It should be fixed at “0”.
2
OBUS
OBUS operation
disabled
0: The OBUS mode is enabled.
1: The OBUS mode is disabled.
R/W
R
1-0 Nothing is placed here. These should be fixed at "0”.
<<Notes>>
*2) The PKTM bit is valid only when the data receiving direction (reading from the buffer memory) is set. If the
DxFIFO port is being used in the data writing direction, “PKTM=0” should be set.
*3) The “DFORM=110” setting is valid only when the DMA channel 0 is set.
Also, the following should not be set: "DFORM=001”,"DFORM=101” and"DFORM=111”.
相關(guān)PDF資料
PDF描述
M68HC11D3CFB1 8-BIT, MROM, 1 MHz, MICROCONTROLLER, PQFP44
M68HC711D0CFN 8-BIT, 2 MHz, MICROCONTROLLER, PQCC44
M68HC711D0CFB 8-BIT, 2 MHz, MICROCONTROLLER, PQFP44
M68HC711D3CFB1 8-BIT, MROM, 1 MHz, MICROCONTROLLER, PQFP44
M68HC711D3CP1 8-BIT, MROM, 1 MHz, MICROCONTROLLER, PDIP40
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M66596FP#RB0Z 制造商:Renesas Electronics Corporation 功能描述:MCU - Trays 制造商:Renesas Electronics 功能描述:USB Device Controller 64-Pin LQFP Cut Tape 制造商:Renesas Electronics 功能描述:USB Device Controller 64-Pin LQFP Tray 制造商:Renesas 功能描述:USB Device Controller 64-Pin LQFP
M66596FPRB0Z 制造商:Renesas Electronics Corporation 功能描述:USB2.0 Dual Function Controller,LQFP64
M66596WG 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:ASSP (USB2.0 Dual Function Controller)
M66596WG#RB0Z 制造商:Renesas Electronics 功能描述:Tray 制造商:Renesas 功能描述:0
M6668 制造商:Tamura Corporation of America 功能描述:
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*