參數(shù)資料
型號: M66596FP
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 0.50 MM PITCH, LQFP-64
文件頁數(shù): 32/131頁
文件大小: 1595K
代理商: M66596FP
M66596FP/WG
rev .1.00
2006.3.14
page 127 of 127
4.10 Interrupt timing
td (CTRL - INT)
Note 7-1
twh (INT)
INT_N
CS_N,
WR0_N, WR1_N
22
21
Note 7-1: Writing using the combination of CS_N, WR0_N and WR1_N takes place during the active (“L”) overlap period.
The ratings from the rising edge are valid starting from the earliest change in the inactive signal.
4.11 Reset timing
tst (RST)
tw (RST)
Note 8-1
RST_N
52
53
CS_N,
WR0_N, WR1_N
Note 8-1: Writing using the combination of CS_N, WR0_N and WR1_N takes place during the active (“L”) overlap period.
The ratings from the rising edge are valid starting from the earliest change in the inactive signal.
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