參數(shù)資料
型號： MAX1358BETL+W
廠商： Maxim Integrated Products
文件頁數(shù)： 17/71頁
文件大?。?/td> 0K
描述： DAS 16BIT DUAL 10:1 40-TQFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 50
類型： 數(shù)據(jù)采集系統(tǒng)（DAS）
分辨率（位）： 16 b
采樣率（每秒）： 21.94k
數(shù)據(jù)接口： MICROWIRE?，QSPI?，串行，SPI?
電壓電源： 模擬和數(shù)字
電源電壓： 1.8 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 40-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 40-TQFN-EP（6x6）
包裝： 托盤
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
24
______________________________________________________________________________________
PIN
NAME
FUNCTION
1
CLK
Clock Output. Default is 2.457MHz output clock for the μC.
2
UPIO2
User-Programmable Input/Output 2. See the UPIO2_CTRL Register section for functionality.
3
UPIO3
User-Programmable Input/Output 3. See the UPIO3_CTRL Register section for functionality.
4
UPIO4
User-Programmable Input/Output 4. See the UPIO4_CTRL Register section for functionality.
5
DOUT
Serial-Data Output. Data is clocked out on SCLK’s falling edge. High impedance when
CS is high, when
UPIO/SPI pass-through mode is enabled, DOUT mirrors the state of UPIO1.
6
SCLK
Serial-Clock Input. Clocks data in and out of the serial interface.
7
DIN
Serial-Data Input. Data is clocked in on SCLK’s rising edge.
8
CS
Active-Low Chip-Select Input. Data is not clocked into DIN unless
CS is low. When CS is high, DOUT is high
impedance. High impedance when
CS is high; when UPIO/SPI pass-through mode is enabled, DOUT
mirrors the state of UPIO1.
9
INT
Programmable Active-High/Low Interrupt Output. ADC, UPIO wake-up, alarm, and voltage-monitor events.
10
CLK32K
32kHz Clock Input/Output. Outputs 32kHz clock for the μC. Can be programmed as an input by enabling
the IO32E bit to accept an external 32kHz input clock. The RTC, PWM, and watchdog timer always use the
internal 32kHz clock derived from the 32kHz crystal.
11
RESET
Active-Low, Open-Drain Reset Output. Remains low while DVDD is below the 1.8V voltage threshold and
stays low for a timeout period (tDSLP) after DVDD rises above the 1.8V threshold.
RESET also pulses low
when the watchdog timer times out and holds low during POR until the 32kHz oscillator stabilizes.
12
32KOUT
32kHz Crystal Output. Connect an external 32kHz watch crystal between 32KIN and 32KOUT.
13
32KIN
32kHz Crystal Input. Connect an external 32kHz watch crystal between 32KIN and 32KOUT.
14
SNO1
Analog Switch 1 Normally Open Terminal. Analog input to mux.
15
SCM1
Analog Switch 1 Common Terminal. Analog input to mux.
16
SNC1
Analog Switch 1 Normally Closed Terminal. Analog input to mux (open on POR).
17
SNO2
Analog Switch 2 Normally Open Terminal. Analog input to mux.
18
SCM2
Analog Switch 2 Common Terminal. Analog input to mux (open on POR).
19
SNC2
Analog Switch 2 Normally Closed Terminal. Analog input to mux.
20
OUT1
Amplifier 1 Output. Analog input to mux.
21
IN1-
Amplifier 1 Inverting Input. Analog input to mux.
22
IN1+
Amplifier 1 Noninverting Input
Pin Description
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