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參數(shù)資料
| 型號： | MAX1358BETL+W |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 51/71頁 |
| 文件大小： | 0K |
| 描述： | DAS 16BIT DUAL 10:1 40-TQFN |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 50 |
| 類型： | 數(shù)據(jù)采集系統(tǒng)（DAS） |
| 分辨率（位）： | 16 b |
| 采樣率（每秒）： | 21.94k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 電壓電源： | 模擬和數(shù)字 |
| 電源電壓： | 1.8 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 40-TQFN-EP（6x6） |
| 包裝： | 托盤 |
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MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
______________________________________________________________________________________
55
The switch-control register controls the two SPDT
switches (SPDT1 and SPDT2) and the DACA output
buffer SPST switch (SWA). Control this switch by the
serial bits in this register, by any of the UPIO pins that
are enabled for that function, or by the PWM.
SWA: DACA output buffer SPST-switch A control bit.
The SWA bit, the UPIO inputs (if configured), and the
PWM (if configured) control the state of the SWA switch
as shown in Table 17. The UPIO_ states of 0 and 1 in the
table correspond to respective deasserted and asserted
logic states as defined by the ALH_ bit of the
UPIO_CTRL register. If a UPIO is not configured for this
mode, its value applied to the table is 0. The PWM
states of 0 and 1 in the table correspond to the respec-
tive PWM off (or low) and on (or high) states defined by
the SWAH and SWAL bits (see the
PWM_CTRL Register
section). If the PWM is not configured for this mode, its
value applied to the table is 0. The power-on default is 0.
SWB: DACB output buffer SPST-switch B control bit.
The SWB bit, the UPIO inputs (if configured), and the
PWM (if configured) control the state of the SWB switch
as shown in Table 18. The UPIO_ states of 0 and 1 in the
table correspond to respective deasserted and asserted
logic states as defined by the ALH_ bit (see the
UPIO_CTRL Register section). If a UPIO is not config-
ured for this mode, its value applied to the table is 0.
The PWM states of 0 and 1 in the table correspond to
the respective PWM off (or low) and on (or high) states
defined by the SWBH and SWBL bits (see the
PWM_CTRL Register section). If the PWM is not config-
ured for this mode, its value applied to the table is 0.
The power-on default is 0.
SPDT1<1:0>: Single-pole double-throw switch 1 con-
trol bits. The SPDT1<1:0> bits, the UPIO pins (if config-
ured), and the PWM (if configured) control the state of
the switch as shown in Table 18. The UPIO_ states of 0
and 1 in the table correspond to respective deasserted
and asserted logic states as defined by the ALH_ bit of
the UPIO_CTRL register. If a UPIO is not configured for
this mode, its value applied to Table 18 is 0. The PWM
states of 0 and 1 in Table 18 correspond to the respec-
tive PWM off (low) and on (high) states defined by the
SPD1 bit in the PWM_CTRL register. If the PWM is not
configured for this mode, its value applied to Table 18
is 0. The power-on default is 00.
MSB
LSB
SWA
SWB
SPDT11
SPDT10
SPDT21
SPDT20
X
SW_CTRL Register (Power-On State: 0000 00XX)
SW_ BIT*
UPIO_*
PWM*
SW_ SWITCH STATE
0
Switch open
X
1
Switch closed
X
1
X
Switch closed
1
X
Switch closed
Table 17. SWA States
X = Don’t care.
*
Switch SW_ control is effectively an OR of the SW_ bit, UPIO_
pins, and PWM.
SPDT1<1:0>
UPIO_*
PWM*
SPDT1 SWITCH STATE
0
SNO1 open, SNC1 open
0
X
1
SNO1 closed, SNC1 closed
0
X
1
X
SNO1 closed, SNC1 closed
0
1
X
SNO1 closed, SNC1 closed
1
0
SNC1 closed, SNO1 open
1
X
1
SNC1 open, SNO1 closed
1
X
1
X
SNC1 open, SNO1 closed
1
X
SNC1 open, SNO1 closed
Table 18. SPDT Switch 1 States
X = Don’t care.
*
Switch SPDT1 control is effectively an OR of the SPDT10 bit, the
UPIO_ pins, and the PWM output. The SPDT11 bit determines if
the switches open and close together or if they toggle.
SPDT2<1:0>
UPIO_* PWM* SPDT2 SWITCH STATE
0
SNO2 open, SNC2 open
0
X
1
SNO2 closed, SNC2 closed
0
X
1
X
SNO2 closed, SNC2 closed
0
1
X
SNO2 closed, SNC2 closed
1
0
SNC2 closed, SNO2 open
1
X
1
SNC2 open, SNO2 closed
1
X
1
X
SNC2 open, SNO2 closed
1
X
SNC2 open, SNO2 closed
Table 19. SPDT Switch 2 States
X = Don’t care.
*
Switch SPDT2 control is effectively an OR of the SPDT20 bit, the
UPIO_ pins, and the PWM output. The SPDT21 bit determines if
the switches open and close together or if they toggle.
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