參數(shù)資料
型號： MAX1358BETL+W
廠商： Maxim Integrated Products
文件頁數(shù)： 40/71頁
文件大?。?/td> 0K
描述： DAS 16BIT DUAL 10:1 40-TQFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 50
類型： 數(shù)據(jù)采集系統(tǒng)（DAS）
分辨率（位）： 16 b
采樣率（每秒）： 21.94k
數(shù)據(jù)接口： MICROWIRE?，QSPI?，串行，SPI?
電壓電源： 模擬和數(shù)字
電源電壓： 1.8 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 40-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 40-TQFN-EP（6x6）
包裝： 托盤
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
______________________________________________________________________________________
45
CLK32K
IO32E
32KIN, 32KOUT
RTC, PWM, WDT
CLOCK SOURCE
FLL, C/P, SDC INPUT
SOURCE
ADC CLOCK SOURCE
Output
1
0
XTAL attached
XTAL
FLL/HFCLK
Input
0
1
XTAL attached
XTAL
CLK32K
FLL/HFCLK
Table 13. Configuring the CLK32K as an Input or Output
HFCE: High-frequency-clock enable bit. Set HFCE = 1
to enable the internal high-frequency clock source, and
set HFCE = 0 to disable the high-frequency clock
source.
If HFCE = 1 and CLKE = 1, the internal high-frequency
oscillator is enabled and is present at CLK. The power-
on default state is 1.
CKSEL<2:0>: Clock selection bits. These bits select
the FLL-based output clock frequency at the high-fre-
quency CLK pin as shown in Table 12. The power-on
default state is 001.
IO32E: Input/output 32kHz clock select bit. Set IO32E
= 0 to configure the CLK32K pin as an output, and set
IO32E = 1 to configure the CLK32K pin as an input,
regardless of the signal on the 32KIN pin as shown in
Table 13.
External clock frequencies applied to CLK32K are
clock sources to the FLL, charge pump, and the signal-
detect comparator. The default power-on state is 0.
CK32E: CLK32K output-buffer enable bit. Set CK32E =
1 to enable the CLK32K output buffer as long as OSCE
= 1 and IO32E = 0; otherwise, the CK32E bit is not
asserted. Set CK32E = 0 to disable the CLK32K output
buffer. The power-on default state is 1.
CLKE: CLK output-buffer enable bit. Set CLKE = 1 to
enable the CLK output buffer. Set CLKE = 0 to disable
the buffer. Disabling the buffer is useful for saving
power in cases where the high-frequency clock is used
internally but is not needed externally. If HFCE = 0, or if
CLKE = 0, CLK remains low. The power-on default
state is 1.
INTP: Interrupt pin polarity bit. Set INTP = 1 to make
INT an active-high output when asserted, and set INTP
= 0 to make INT an active-low output when asserted.
The power-on default state is 1.
WDE: Watchdog-enable bit. Set WDE = 1 to enable the
watchdog timer, which asserts
RESET low within 500ms
if the WATCHDOG register is not written. Set WDE = 0
to disable the watchdog timer. The power-on default
state is 0.
CLOCK FREQUENCY
(kHz)
CKSEL2
CKSEL1
CKSEL0
4915.2
0
2457.6
0
1
1228.8
0
1
0
614.4
0
1
32.768
1
0
16.384
1
0
1
8.192
1
0
4.096
1
Table 12. Setting the CLK Frequency
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