參數(shù)資料
型號(hào): MAX1441GUP/V+
廠商: Maxim Integrated Products
文件頁數(shù): 15/41頁
文件大?。?/td> 0K
描述: IC PROXMITY SENSOR 2CH 20-TSSOP
其它有關(guān)文件: Automotive Product Guide
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 74
類型: 觸控式傳感器
輸入類型: 數(shù)字
輸出類型: 數(shù)字
接口: JTAG,串行
電流 - 電源: 100µA
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 管件
MAX1441
Automotive, Two-Channel Proximity and
Touch Sensor
22
Table 10. Special-Function Register Reset Values
Table 11. Special-Function Register Bit Description
MODULE 0
MODULE 1
REGISTER
MSB
LSB
REGISTER
MSB
LSB
PO0
0111
1111
AFEINTST
0000
EIF0
0000
SCT
0000
0010
EIE0
0000
CRNG
0010
EIES0
0000
PD
0000
TCON
0000
WU1
0000
0100
TFRQ
0000
WU2
0000
0100
TCNT
0000
FEL
0001
1110
PI0
ssss
FEB
0000
PD0
0000
CRSLT1L
0000
BRKP
0000
CRSLT1H
0000
ICDT0
0000
CRSLT2L
0000
ICDT1
0000
CRSLT2H
0000
ICDC
0000
AT1H
0000
ICDF
0000
RT1H
0000
ICDB
0000
AT2H
0000
ICDA
0000
RT2H
0000
ICDD
0000
CO1
0000
CO2
0000
DSB
0000
0001
SSB2
0000
0001
AFEIE
0000
REGISTER
DESCRIPTION
PO0 (00h, 00h)
Port 0 Output Register (8-Bit Register)
Initialization
This register is set to 7Fh on all forms of reset.
Read/Write Access
Unrestricted read/write.
PO0[6:0]
Port 0 Output Register Bits [6:0]. This register stores output data for this port when it is defined as
an output port. Reading from the register returns the contents of the register and does not necessarily
reflect the true state of the port pins. Changing the direction of this port does not change the data con-
tents of the register.
PO0.7
Reserved. Read returns 0.
EIF0 (01h, 00h)
External Interrupt Flag 0 Register (8-Bit Register)
Initialization
This register is cleared to 00h on all forms of reset.
Read/Write Access
Unrestricted read/write.
EIF0[2:0]–IE[2:0]
Interrupt Edge Detect Bits [2:0]. These bits are set when the edge selected by ITx is detected on the
interrupt pin, INTx. Setting any of the bits to 1 generates an interrupt to the CPU if the corresponding
interrupt is enabled. These bits remain set until cleared by software or a reset. It must be cleared by
software before exiting the interrupt source routine or another interrupt is generated as long as the bit
remains set.
EIF0[7:3]
Reserved. Read returns 0.
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