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參數(shù)資料
| 型號(hào)： | MAX1441GUP/V+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 3/41頁 |
| 文件大小： | 0K |
| 描述： | IC PROXMITY SENSOR 2CH 20-TSSOP |
| 其它有關(guān)文件： | Automotive Product Guide |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 74 |
| 類型： | 觸控式傳感器 |
| 輸入類型： | 數(shù)字 |
| 輸出類型： | 數(shù)字 |
| 接口： | JTAG，串行 |
| 電流 - 電源： | 100µA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 管件 |
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MAX1441
Automotive, Two-Channel Proximity and
Touch Sensor
11
Power-Down Control
Each sensor channel independently powers down
through the PD register. Bit value 1 powers down the
channel and bit value 0 powers up the channel. The
excitation source circuitry powers down if both chan-
nels are powered down. Powering down both channels
also resets all AFE internal circuits except for the AFE’s
control registers.
Wake-Up Event Thresholds
The sensor wakes up when the measured capacitance
exceeds a set capacitance threshold and/or a pre-
defined rate of change in the capacitance. When an
object approaches the sensor, the sensed capacitance
starts changing. Once the capacitance value crosses
the absolute value threshold and/or the capacitance
rate of change crosses the rate-of-change threshold, the
analog front-end is automatically put in the wake-up state
and the SB bit is cleared. At the same time, the wake-up
interrupt is sent to the microcontroller. The 8-bit word
ATx[11:4] determines the absolute wake-up threshold
and 8-bit word RTx[11:4] determines the rate-of-change
threshold. Only the upper 8 bits are used in the thresh-
old comparisons. Bit AOx determines if logical AND
or OR operation is performed on the absolute and the
rate-of-change threshold crossing events to produce the
wake-up event. Bit value 1 sets the AND operation and
bit value 0 sets OR operation. Both absolute and rate-
of-change threshold crossing detection can be enabled
or disabled using bits AEx and REx. AEx bit value 1
enables absolute value detection and REx bit value 1
enables rate-of-change detection. The thresholds can be
independently programmed in channels 1 and 2.
Conversion Result Word
The 12-bit result of the C2D conversion is available in
CRSLT1L and CRSLT1H for channel 1 and in CRSLT2L
and CRSLT2H for channel 2. Bit OVRx is set to 1 if the cur-
rent conversion caused overranging in the C2D converter.
Data Ready in Channel 1
The interrupt status bit IDR1 is set to 1 when a new
conversion result is available in channel 1. If the micro-
controller does not read the conversion result before the
next conversion is completed, the old conversion result
is overwritten.
Data Ready in Channel 2
The interrupt status bit IDR2 is set to 1 when a the new
conversion result is available in channel 2. If the micro-
controller does not read the conversion result before the
next conversion is completed, the old conversion result
is overwritten.
Wake-Up Event in Channel 1
The interrupt status bit IWUP1 is set to 1 when channel 1
detects a wake-up condition.
Wake-Up Event in Channel 2
The interrupt status bit IWUP2 is set to 1 when channel 2
detects a wake-up condition.
Detailed Controller Specification
Architecture
The device is based on the MAXQ RISC processor with
Harvard memory architecture.
Specific MAXQ Special-Purpose
Register Implementation
The device implements all other standard MAXQ special-
purpose registers (SPRs). For details, see the SPR bit
description in Table 5.
Special-Purpose Registers
Table 2 summarizes the SPRs and their address indexes.
These registers can be accessed by user software.
Table 2. Special-Purpose Register Map
MODULE
INDEX OF SPECIAL-PURPOSE REGISTER
MODULE SPECIFIER 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101
01110
01111
AP
01000
AP
APC
—
PSF
IC
IMR
—
SC
—
IIR
—
CKCN
WDCN
A
01001
A0
A1
A2
A3
—
PFX
01011
PFX
—
IP
01100
IP
—
SP
01101
—
SP
IV
—
LC0
LC1
—
DPC
01110
—
Offs
DPC
GR
GRL
BP
GRS
GRH
GRXL
FP
—
DP
01111
—
DP0
—
DP1
—
CP
—
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