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| 型號： | MAX1441GUP/V+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 19/41頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROXMITY SENSOR 2CH 20-TSSOP |
| 其它有關(guān)文件： | Automotive Product Guide |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 74 |
| 類型： | 觸控式傳感器 |
| 輸入類型： | 數(shù)字 |
| 輸出類型： | 數(shù)字 |
| 接口： | JTAG，串行 |
| 電流 - 電源： | 100µA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 管件 |
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MAX1441
Automotive, Two-Channel Proximity and
Touch Sensor
26
Table 11. Special-Function Register Bit Description (continued)
REGISTER
DESCRIPTION
ICDF[7:2]
Reserved. Read returns 0.
ICDB (1Ch, 00h)
In-Circuit Debug Buffer Register (8-Bit Register)
Initialization
This register is cleared to 00h after a power-on reset or a Test-Logic-Reset TAP state.
Read/Write Access
Unrestricted read/write by CPU.
ICDB[7:0]
In-Circuit Debug Buffer Bits [7:0]. ICDB serves as the parallel holding buffer for the debug shift
register of the TAP. Data is read from or written to ICDB for serial communication between the debug
function and the external host. This register is mapped to the SFR space for read/write access by the
CPU.
ICDA (1Dh, 00h)
In-Circuit Debug Address Register (16-Bit Register)
Initialization
This register is cleared to FFFFh after a power-on reset or a Test-Logic-Reset TAP state.
Read/Write Access
Unrestricted read by the CPU. This register can be accessed using a valid JTAG debug engine command.
ICDA[15:0]
In-Circuit Debug Address Bits [15:0]. This register serves as the address register for the debug engine
to store a specific location for the ROM code execution. This register is also used by the debug engine
as a mask register to mask out don’t care bits in the ICDD register when BP5 is used as a register
breakpoint. When a bit in this register is set to 1, the corresponding bit location in the ICDD register is
compared to the updating destination data to determine if a break should be generated. When a bit
in this register is cleared, the corresponding bit in the ICDD register becomes a don’t care and is not
compared against the updating data. When all bits in this register are cleared, any updated data pattern
causes a break when the BP5 register matches the destination register address of the current
instruction.
ICDD (1Eh, 00h)
In-Circuit Debug Data Register (16-Bit Register)
Initialization
This register is cleared to 0000h after a power-on reset or a Test-Logic-Reset TAP state.
Read/Write Access
Unrestricted read by the CPU. This register can be accessed using a valid JTAG debug engine command.
ICDD[15:0]
In-Circuit Debug Data Bits [15:0]. This register serves as the data/count register for the debug engine
to store data or read count for ROM code execution. This register is also used by the debug engine as a
data register for content matching when BP5 is used as a register breakpoint. In this case, only data bits
in this register with their corresponding mask bits in the ICDA register set is compared with the updated
destination data to determine if a break should be generated.
AFEINTST (00h, 01h) AFE Interrupt Status Register (8-Bit Register)
Initialization
This register is cleared to 00h on all forms of reset.
Read/Write Access
Unrestricted read/write. See the following individual bit definitions for write restriction.
AFEINTST.0–IDR1
CH1 Data Ready Interrupt Flag. This bit is set to 1 when a new conversion result is available. This bit
remains set unless cleared by software.
AFEINTST.1–IDR2
CH2 Data Ready Interrupt Flag. This bit is set to 1 when a new conversion result is available. This bit
remains set unless cleared by software.
AFEINTST.2–IWUP1
CH1 Wake-Up Event Interrupt Flag. This bit is set to 1 when a wake-up condition is detected. This bit
remains set unless cleared by software.
AFEINTST.3–IWUP2
CH2 Wake-Up Event Interrupt Flag. This bit is set to 1 when a wake-up condition is detected. This bit
remains set unless cleared by software.
AFEINTST[7:4]
Reserved. Read returns 0.
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