參數(shù)資料
型號: MAX1441GUP/V+
廠商: Maxim Integrated Products
文件頁數(shù): 22/41頁
文件大?。?/td> 0K
描述: IC PROXMITY SENSOR 2CH 20-TSSOP
其它有關(guān)文件: Automotive Product Guide
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 74
類型: 觸控式傳感器
輸入類型: 數(shù)字
輸出類型: 數(shù)字
接口: JTAG,串行
電流 - 電源: 100µA
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 管件
MAX1441
Automotive, Two-Channel Proximity and
Touch Sensor
29
Table 11. Special-Function Register Bit Description (continued)
REGISTER
DESCRIPTION
CRSLT1H (09h, 01h)
Channel 1 Conversion Result Register (8-Bit Register)
Initialization
This register is cleared to 00h on all forms of reset.
Read/Write Access
This register is read-only.
CRSLT1H[7:0]
Channel 1 Conversion Result Bits [11:4]. This register contains the upper 8 bits of the C–to–D
conversion.
CRSLT2L (0Ah, 01h)
Channel 2 Conversion Result Register (8-Bit Register)
Initialization
This register is cleared to 00h on all forms of reset.
Read/Write Access
This register is read-only.
CRSLT2L.0–OVR2
CH2 Overrange Flag. The overrange flag is set to 1 by hardware if the current conversion causes
overranging of the C–to–D conversion. This bit is cleared to 0 if the current conversion does not cause
overranging.
CRSLT2L[3:0]
Reserved. Read returns 0.
CRSLT2L[7:4]
Channel 2 Conversion Result Bits [3:0]. This register contains the lower 4 bits of the C–to–D
conversion.
CRSLT2H (0Bh, 01h)
Channel 2 Conversion Result Register (8-Bit Register)
Initialization
This register is cleared to 00h on all forms of reset.
Read/Write Access
This register is read only.
CRSLT2H[7:0]
Channel 2 Conversion Result Bits [11:4]. This register contains the upper 8 bits of the C–to–D
conversion.
AT1H (0Ch, 01h)
CH1 Absolute Wake-Up Threshold Register (8-Bit Register)
Initialization
This register is cleared to 00h on all forms of reset.
Read/Write Access
Unrestricted read/write.
AT1H[7:0]
CH1 Absolute Wake-Up Threshold Bits [11:4]. This register contains the threshold value against
which a wake-up event is generated in standby mode. This register has no effect if the absolute
threshold is not enabled.
RT1H (0Dh, 01h)
CH1 Rate-of-Change Wake-Up Threshold Register (8-Bit Register)
Initialization
This register is cleared to 0000h on all forms of reset.
Read/Write Access
Unrestricted read/write.
RT1H[7:0]
CH1 Rate-of-Change Wake-Up Threshold Bits [11:4]. This register contains the threshold value
against which a wake-up event is generated in standby mode. This register has no effect if the
rate-of-change threshold is not enabled.
AT2H (0Eh, 01h)
CH2 Absolute Wake-Up Threshold Register (8-Bit Register)
Initialization
This register is cleared to 0000h on all forms of reset.
Read/Write Access
Unrestricted read/write.
AT2H[7:0]
CH2 Absolute Wake-Up Threshold Bits [11:4]. This register contains the threshold value against
which a wake-up event is generated in standby mode. This register has no effect if the absolute
threshold is not enabled.
RT2H (0Fh, 01h)
CH2 Rate-of-Change Wake-Up Threshold Register (8-Bit Register)
Initialization
This register is cleared to 0000h on all forms of reset.
Read/Write Access
Unrestricted read/write.
RT2H[7:0]
CH2 Rate-of-Change Wake-Up Threshold Bits [11:4]. This register contains the threshold value
against which a wake-up event is generated in standby mode. This register has no effect if the
rate-of-change threshold is not enabled.
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