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參數(shù)資料
| 型號： | MAX1441GUP/V+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 18/41頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROXMITY SENSOR 2CH 20-TSSOP |
| 其它有關(guān)文件： | Automotive Product Guide |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 74 |
| 類型： | 觸控式傳感器 |
| 輸入類型： | 數(shù)字 |
| 輸出類型： | 數(shù)字 |
| 接口： | JTAG，串行 |
| 電流 - 電源： | 100µA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 管件 |
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MAX1441
Automotive, Two-Channel Proximity and
Touch Sensor
25
Table 11. Special-Function Register Bit Description (continued)
REGISTER
DESCRIPTION
ICDC (1Ah, 00h)
In-Circuit Debug Control Register (8-Bit Register)
Initialization
This register is cleared to 00h after a power-on reset or a Test-Logic-Reset TAP state.
Read/Write Access
Unrestricted read; all bits are set and cleared by the debug engine only. This register can be accessed
using a valid JTAG debug engine command.
ICDC[3:0]–CMD[3:0]
Command Bits [3:0]. These bits reflect the current host command in debug mode. These bits are set
by the debug engine and allow the ROM code to determine the course of action.
CMD[3:0]
ACTION
0000
No operation
0001
Read register
0010
Read data memory
0011
Read stack memory
0100
Write register
0101
Write data memory
0110
Trace, single step the CPU
0111
Return, return to background mode
1000
Unlock password
1001
Read selected register
1010
Execute Test Execute Test (only supported when TME = 1)
Other
Reserved
ICDC.4
Reserved. Read returns 0.
ICDC.5–REGE
Break-On Register Enable.
This bit always returns 0. Therefore, BP4 and BP5 breakpoints are not supported.
ICDC.6–TE
Timer Enabled.
This bit always returns 0 and the timer is automatically disabled in debug mode.
ICDC.7–DME
Debug Mode Enable. When this bit is cleared to 0, background mode commands can be executed but
breakpoints are disabled. When this bit is set to 1, breakpoints are enabled while background mode
commands can still be entered. This bit is only set or cleared from background mode. This bit has no
meaning for the ROM code.
ICDF (1Bh, 00h)
In-Circuit Debug Flag Register (8-Bit Register)
Initialization
This register is cleared to 00h after a power-on reset or a Test-Logic-Reset TAP state.
Read/Write Access
Unrestricted read; only bit 0 is writable by the CPU.
ICDF.0–TXC
Serial Transfer Complete. This bit is set by the hardware at the end of a transfer cycle at the TAP
communication link. The TXC helps the debug engine to recognize host requests, either command or
data. This bit is normally set by ROM code to signify/request sending or receiving data; the TXC must
be cleared by the debug engine once set. CPU writes to the TXC bit result in clearing the JTAG PSS1:0
bits.
ICDF.1–SPE
System Program Enable. The SPE bit used for in-system programming support and its logical state,
when read by the CPU, always reflects the logical-OR of the SPE bit and the SPE bit of the System
Programming Buffer (SPB) register in the TAP module (which is accessible using JTAG). The logical
state of this bit determines the program flow after a reset. When it is set to logic 1, in-system program-
ming is executed by the utility ROM. When it is cleared to 0, execution is transferred to user code. This
bit allows read access by the CPU and is cleared to 0 only on a power-on reset or Test-Logic-Reset. The
JTAG SPE bit is cleared by hardware when the ROD bit is set.
The SPE bit is read only.
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| MAX1444EHJ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1444EHJ/V+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC ANALOG TO DIGITAL CONVERTER RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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