參數(shù)資料
型號: MC56F8356VFV60
廠商: MOTOROLA INC
元件分類: 數(shù)字信號處理
英文描述: 56F8356 16-bit Hybrid Controller
中文描述: 16-BIT, 120 MHz, OTHER DSP, PQFP144
封裝: LQFP-144
文件頁數(shù): 115/160頁
文件大?。?/td> 1380K
代理商: MC56F8356VFV60
Flash Access Blocking Mechanisms
56F8356 Technical Data
Preliminary
115
7.2.2
On-chip Flash can be read by issuing commands across the EOnCE port, which is the debug
interface for the 56800E core. The TRST, TCLK, TMS, TDO, and TDI pins comprise a JTAG
interface onto which the EOnCE port functionality is mapped. When the 56F8356 boots, the
chip-level JTAG TAP (Test Access Port) is active and provides the chip’s boundary scan capability
and access to the ID register.
Disabling EOnCE Access
Proper implementation of Flash security requires that no access to the EOnCE port is provided
when security is enabled. The 56800E core has an input which disables reading of internal memory
via the JTAG/EOnCE. The FM sets this input at reset to a value determined by the contents of the
FM security bytes.
7.2.3
If a user inadvertently enables security on the 56F8356, a lockout recovery mechanism is provided
which allows the complete erasure of the internal Flash contents, including the configuration field,
and thus disables security (the protection register is cleared). This does not compromise security,
as the entire contents of the user’s secured code stored in Flash are erased before security is
disabled on the 56F8356 on the next reset or power-up sequence. To start the lockout recovery
sequence, the JTAG public instruction (LOCKOUT_RECOVERY) must first be shifted into the
chip-level TAP controller’s instruction register.
Flash LOCKOUT_RECOVERY
The LOCKOUT_RECOVERY instruction will have an associated 7-bit Data Register (DR) that is
used to control the clock divider circuit within the FM module. This divider, FM_CLKDIV[6:0],
is used to control the period of the clock used for timed events in the FM erase algorithm. This
register must be set with appropriate values before the lockout sequence can begin. Refer to the
JTAG section of the
56F8300 Peripheral User Manual
for more details on setting this register
value.
The value of the JTAG FM_CLKDIV[6:0] will replace the value of the FM register FMCLKD that
divides down the system clock for timed events, as illustrated in
Figure 7-1
. FM_CLKDIV[6] will
map to the PRDIV8 bit, and FM_CLKDIV[5:0] will map to the DIV[5:0] bits. The combination of
PRDIV8 and DIV must divide the FM input clock down to a frequency of 150kHz-200kHz. The
“Writing the FMCLKD Register
” section in the Flash Memory chapter of the
56F8300
Peripheral User Manual
gives specific equations for calculating the correct values.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
相關(guān)PDF資料
PDF描述
MC56F8356MFV60 56F8356 16-bit Hybrid Controller
MC56F8357 16-bit Digital Signal Processor
MC56F8357 16-BIT HYBRID CONTROLLERS
MC56F8357MPY60 16-bit Digital Signal Processor
MC56F8357VPY60 16-bit Digital Signal Processor
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