參數(shù)資料
型號(hào): MC56F8356VFV60
廠商: MOTOROLA INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 56F8356 16-bit Hybrid Controller
中文描述: 16-BIT, 120 MHz, OTHER DSP, PQFP144
封裝: LQFP-144
文件頁數(shù): 21/160頁
文件大?。?/td> 1380K
代理商: MC56F8356VFV60
56F8356 Signal Pins
56F8356 Technical Data
Preliminary
21
TXD0
(GPIOE0)
4
Output
Input/
Output
Tri-stated
Input
Transmit Data
— SCI0 transmit data output
Port E GPIO
— This GPIO pin can be individually
programmed as an input or output pin.
After reset, the default state is SCI output.
To deactivate the internal pull-up resistor, clear bit 0 in the
GPIOE_PUR register.
RXD0
(GPIOE1)
5
Input
Input/
Output
Input
Input
Receive Data
— SCI0 receive data input
Port E GPIO
— This GPIO pin can be individually
programmed as an input or output pin.
After reset, the default state is SCI output.
To deactivate the internal pull-up resistor, clear bit 1 in the
GPIOE_PUR register.
TXD1
(GPIOD6)
42
Output
Input/
Output
Tri-stated
Input
Transmit Data
— SCI1 transmit data output
Port D GPIO
— This GPIO pin can be individually
programmed as an input or output pin.
After reset, the default state is SCI output.
To deactivate the internal pull-up resistor, clear bit 6 in the
GPIOD_PUR register.
RXD1
(GPIOD7)
43
Input
Input/
Output
Input
Input
Receive Data
— SCI1 receive data input
Port D GPIO
— This GPIO pin can be individually
programmed as an input or output pin.
After reset, the default state is SCI input.
To deactivate the internal pull-up resistor, clear bit 7 in the
GPIOD_PUR register.
TCK
121
Schmitt
Input
Input,
pulled low
internally
Test Clock Input
— This input pin provides a gated clock
to synchronize the test logic and shift serial data to the
JTAG/EOnCE port. The pin is connected internally to a
pull-down resistor.
TMS
122
Schmitt
Input
Input,
pulled high
internally
Test Mode Select Input
— This input pin is used to
sequence the JTAG TAP controller’s state machine. It is
sampled on the rising edge of TCK and has an on-chip
pull-up resistor.
To deactivate the internal pull-up resistor, set the JTAG bit
in the SIM_PUDR register.
Table 2-2 56F8356 Signal and Package Information for the 144-Pin LQFP
Signal Name
Pin No.
Type
State
During
Reset
Signal Description
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
相關(guān)PDF資料
PDF描述
MC56F8356MFV60 56F8356 16-bit Hybrid Controller
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