參數(shù)資料
型號: MC56F8356VFV60
廠商: MOTOROLA INC
元件分類: 數(shù)字信號處理
英文描述: 56F8356 16-bit Hybrid Controller
中文描述: 16-BIT, 120 MHz, OTHER DSP, PQFP144
封裝: LQFP-144
文件頁數(shù): 35/160頁
文件大?。?/td> 1380K
代理商: MC56F8356VFV60
Program Map
56F8356 Technical Data
Preliminary
35
4.2 Program Map
The operating mode control bits (MA and MB) in the Operating Mode Register (OMR) control the
Program memory map. At reset, these bits are set as indicated in
Table 4-2
.
Table 4-4
shows the
memory map configurations that are possible at reset. After reset, the OMR MA bit can be changed
and will have an effect on the P-space memory map, as shown in
Table 4-3
. Changing the OMR
MB bit will have no effect.
The 56F8356’s external memory interface (EMI) can operate much like the 56F80x family’s EMI,
or it can be operated in a mode similar to that used on other products in the 56800E family. Initially,
CS0 and CS1 are configured as PS and DS, in a mode compatible with earlier 56800 devices.
Eighteen address lines are required to shadow the first 192K of internal program space when
booting externally for development purposes. Therefore, the entire complement of on-chip
memory cannot be accessed using a 16-bit 56800-compatible address bus. To address this
situation, the EMI_MODE pin can be used to configure four GPIO pins as Address[19:16] upon
reset (only one of these pins [A16] is usable in the 56F8356).
The EMI_MODE pin also affects the reset vector address, as provided in
Table 4-4
.
Additional
pins must be configured as address or chip select signals to access addresses at P:$10 0000 and
above.
Table 4-2 OMR MB/MAL Value at Reset
OMR MB =
Flash Secured
State
1,
2
1.
This bit is only configured at reset. If the Flash secured state changes, this will not be reflected in MB until the next reset.
2.
Changing MB in software will not affect Flash memory security.
OMR MA =
EXTBOOT Pin
Chip Operating Mode
0
0
Mode 0 – Internal Boot; EMI is configured to use 16 address lines; Flash
Memory is secured; external P-space is not allowed; the EOnCE is disabled
0
1
Not valid; cannot boot externally if the Flash is secured and will actually
configure to 00 state
1
0
Mode 0 – Internal Boot; EMI is configured to use 16 address lines
1
1
Mode 1 – External Boot; Flash Memory is not secured; EMI configuration is
determined by the state of the EMI_MODE pin
Table 4-3 Changing OMR MA Value During Normal Operation
OMR MA
Chip Operating Mode
0
Use internal P-space memory map configuration
1
Use external P-space memory map configuration – If MB = 0 at reset, changing this bit has no
effect.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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