MC68336/376
TIME PROCESSOR UNIT
MOTOROLA
USER’S MANUAL
Rev. 15 Oct 2000
11-15
T2CG is cleared, an external clock from the TCR2 pin, which has been synchronized
and fed through a digital filter, increments TCR2.
The TCR2 field in TPUMCR specifies the value of the prescaler: 1, 2, 4, or 8. Channels
using TCR2 have the capability to resolve down to the TPU system clock divided by
eight. Table 11-2 is a summary of prescaler output.
11.6.1.3 Emulation Control
Asserting the EMU bit in TPUMCR places the TPU in emulation mode. In emulation
mode, the TPU executes microinstructions from TPURAM exclusively. Access to the
TPURAM module through the IMB is blocked, and the TPURAM module is dedicated
for use by the TPU. After reset, EMU can be written only once.
11.6.1.4 Low-Power Stop Control
If the STOP bit in TPUMCR is set, the TPU shuts down its internal clocks, shutting
down the internal microengine. TCR1 and TCR2 cease to increment and retain the last
value before the stop condition was entered. The TPU asserts the stop flag (STF) in
TPUMCR to indicate that it has stopped.
11.6.2 Channel Control Registers
The channel control and status registers enable the TPU to control channel interrupts,
assign time functions to be executed on a specified channel, or select the mode of
operation or the type of host service request for the time function specified. Refer to
11.6.2.1 Channel Interrupt Enable and Status Registers
The channel interrupt enable register (CIER) allows the CPU32 to enable or disable
the ability of individual TPU channels to request interrupt service. Setting the appropri-
ate bit in the register enables a channel to make an interrupt service request; clearing
a bit disables the interrupt.
The channel interrupt status register (CISR) contains one interrupt status flag per
channel. Time functions specify via microcode when an interrupt flag is set. Setting a
flag causes the TPU to make an interrupt service request if the corresponding CIER
bit is set and the CIRL field has a non-zero value. To clear a status flag, read CISR,
then write a zero to the appropriate bit. CISR is the only TPU register that can be
accessed on a byte basis.
Table 11-2 TCR2 Prescaler Control
TCR2 Prescaler
Divide By
Internal Clock
Divided By
External Clock
Divided By
00
1
8
1
01
2
16
2
10
4
32
4
11
8
64
8