MC68336/376
SYSTEM INTEGRATION MODULE
MOTOROLA
USER’S MANUAL
Rev. 15 Oct 2000
5-47
being aborted by reset. While RESET is asserted, SIM pins are either in an inactive,
high-impedance state or are driven to their inactive states.
When an external device asserts RESET for the proper period, reset control logic
clocks the signal into an internal latch. The control logic drives the RESET pin low for
an additional 512 CLKOUT cycles after it detects that the RESET signal is no longer
being externally driven to guarantee this length of reset to the entire system.
If an internal source asserts a reset signal, the reset control logic asserts the RESET
pin for a minimum of 512 cycles. If the reset signal is still asserted at the end of 512
cycles, the control logic continues to assert the RESET pin until the internal reset sig-
nal is negated.
After 512 cycles have elapsed, the RESET pin goes to an inactive, high-impedance
state for ten cycles. At the end of this 10-cycle period, the RESET input is tested. When
the input is at logic level one, reset exception processing begins. If, however, the
RESET input is at logic level zero, reset control logic drives the pin low for another 512
cycles. At the end of this period, the pin again goes to high-impedance state for ten
cycles, then it is tested again. The process repeats until RESET is released.
5.7.7 Power-On Reset
When the SIM clock synthesizer is used to generate system clocks, power-on reset
involves special circumstances related to application of system and clock synthesizer
power. Regardless of clock source, voltage must be applied to the clock synthesizer
power input pin VDDSYN for the MCU to operate. The following discussion assumes
that VDDSYN is applied before and during reset, which minimizes crystal start-up time.
When VDDSYN is applied at power-on, start-up time is affected by specific crystal
parameters and by oscillator circuit design. VDD ramp-up time also affects pin state
and timing specifications.
During power-on reset, an internal circuit in the SIM drives the IMB internal (MSTRST)
and external (EXTRST) reset lines. The power-on reset circuit releases the internal
reset line as VDD ramps up to the minimum operating voltage, and SIM pins are initial-
ized to the values shown in Table 5-17. When VDD reaches the minimum operating voltage, the clock synthesizer VCO begins operation. Clock frequency ramps up to
specified limp mode frequency (flimp). The external RESET line remains asserted until
the clock synthesizer PLL locks and 512 CLKOUT cycles elapse.
The SIM clock synthesizer provides clock signals to the other MCU modules. After the
clock is running and MSTRST is asserted for at least four clock cycles, these modules
reset. VDD ramp time and VCO frequency ramp time determine how long the four
cycles take. Worst case is approximately 15 milliseconds. During this period, module
port pins may be in an indeterminate state. While input-only pins can be put in a known
state by external pull-up resistors, external logic on input/output or output-only pins
during this time must condition the lines. Active drivers require high-impedance buffers
or isolation resistors to prevent conflict.