MC68336/376
SYSTEM INTEGRATION MODULE
MOTOROLA
USER’S MANUAL
Rev. 15 Oct 2000
5-39
SIZ[1:0] signals reflect bus allocation during show cycles. Only the appropriate portion
of the data bus is valid during the cycle. During a byte write to an internal address, the
portion of the bus that represents the byte that is not written reflects internal bus con-
ditions, and is indeterminate. During a byte write to an external address, the data
multiplexer in the SIM causes the value of the byte that is written to be driven out on
both bytes of the data bus.
5.7 Reset
Reset occurs when an active low logic level on the RESET pin is clocked into the SIM.
The RESET input is synchronized to the system clock. If there is no clock when
RESET is asserted, reset does not occur until the clock starts. Resets are clocked to
allow completion of write cycles in progress at the time RESET is asserted.
Reset procedures handle system initialization and recovery from catastrophic failure.
The MCU performs resets with a combination of hardware and software. The SIM
determines whether a reset is valid, asserts control signals, performs basic system
configuration and boot ROM selection based on hardware mode-select inputs, then
passes control to the CPU32.
5.7.1 Reset Exception Processing
The CPU32 processes resets as a type of asynchronous exception. An exception is
an event that preempts normal processing, and can be caused by internal or external
events. Exception processing makes the transition from normal instruction execution
to execution of a routine that deals with an exception. Each exception has an assigned
vector that points to an associated handler routine. These vectors are stored in the
exception vector table. The exception vector table consists of 256 four-byte vectors
and occupies 1024 bytes of address space. The exception vector table can be relo-
cated in memory by changing its base address in the vector base register (VBR). The
CPU32 uses vector numbers to calculate displacement into the table. Refer to 4.9 Reset is the highest-priority CPU32 exception. Unlike all other exceptions, a reset
occurs at the end of a bus cycle, and not at an instruction boundary. Handling resets
in this way prevents write cycles in progress at the time the reset signal is asserted
from being corrupted. However, any processing in progress is aborted by the reset
exception and cannot be restarted. Only essential reset tasks are performed during
exception processing. Other initialization tasks must be accomplished by the excep-
tion handler routine. Refer to 5.7.9 exception processing.
5.7.2 Reset Control Logic
SIM reset control logic determines the cause of a reset, synchronizes reset assertion
if necessary to the completion of the current bus cycle, and asserts the appropriate re-
set lines. Reset control logic can drive four different internal signals: