MC68336/376
SYSTEM INTEGRATION MODULE
MOTOROLA
USER’S MANUAL
Rev. 15 Oct 2000
5-58
The chip-select address compare logic uses only the most significant bits to match an
address within a block. The value of the base address must be an integer multiple of
the block size.
After reset, the MCU fetches the initialization routine from the address contained in the
reset vector, located beginning at address $000000 of program space. To support
bootstrap operation from reset, the base address field in the boot chip-select base
address register (CSBARBT) has a reset value of $000, which corresponds to a base
address of $000000 and a block size of one Mbyte. A memory device containing the
reset vector and initialization routine can be automatically enabled by CSBOOT after
5.9.1.3 Chip-Select Option Registers
Option register fields determine timing of and conditions for assertion of chip-select
signals. To assert a chip-select signal, and to provide DSACK or autovector support,
other constraints set by fields in the option register and in the base address register
must also be satisfied. The following paragraphs summarize option register functions.
The MODE bit determines whether chip-select assertion simulates an asynchronous
bus cycle, or is synchronized to the M6800-type bus clock signal ECLK available on
BYTE[1:0] controls bus allocation for chip-select transfers. Port size, set when a chip-
select is enabled by a pin assignment register, affects signal assertion. When an 8-bit
port is assigned, any BYTE field value other than %00 enables the chip-select signal.
When a 16-bit port is assigned, however, BYTE field value determines when the chip-
select is enabled. The BYTE fields for CS[10:0] are cleared during reset. However,
both bits in the boot ROM chip-select option register (CSORBT) BYTE field are set
(%11) when the RESET signal is released.
R/W[1:0] causes a chip-select signal to be asserted only for a read, only for a write, or
for both read and write. Use this field in conjunction with the STRB bit to generate
asynchronous control signals for external devices.
Table 5-20 Block Size Encoding
BLKSZ[2:0]
Block Size
Address Lines Compared
000
2 Kbytes
ADDR[23:11]
001
8 Kbytes
ADDR[23:13]
010
16 Kbytes
ADDR[23:14]
011
64 Kbytes
ADDR[23:16]
100
128 Kbytes
ADDR[23:17]
101
256 Kbytes
ADDR[23:18]
110
512 Kbytes
ADDR[23:19]
111
1 Mbyte
ADDR[23:20]