MC68336/376
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE
MOTOROLA
USER’S MANUAL
Rev. 15 Oct 2000
8-25
Figure 8-8 shows that the prescaler is essentially a variable pulse width signal gener-
ator. A 5-bit down counter, clocked at the system clock rate, is used to create both the
high phase and the low phase of the QCLK signal. At the beginning of the high phase,
the 5-bit counter is loaded with the 5-bit PSH value. When the zero detector finds that
the high phase is finished, QCLK is reset. A 3-bit comparator looks for a one’s com-
plement match with the 3-bit PSL value, which is the end of the low phase of QCLK.
The PSA bit allows the QCLK high-to-low transition to be delayed by a half cycle of the
input clock.
The following sequence summarizes the process of determining what values are to be
put into the prescaler fields in QACR0:
1. Choose the system clock frequency f
sys.
2. Choose first-try values for PSH, PSL, and PSA, then skip to step 4.
3. Choose different values for PSH, PSL, and PSA.
4. If the QCLK high time is less than t
PSH (QADC clock duty cycle – Minimum high
phase time), return to step 3. Refer to Table A-13 for more information on t
PSH.
QCLK high time is determined by the following equation:
where PSH = 0 to 31 and PSA = 0 or 1.
5. If QCLK low time is less than t
PSL (QADC clock duty cycle – Minimum low phase
time), return to step 3. Refer to Table A-13 for more information on t
PSL.
QCLK
low time is determined by the following equation:
where PSL = 0 to 7 and PSA = 0 or 1.
6. Calculate the QCLK frequency (f
QCLK
).
7. Choose the number of input sample cycles (2, 4, 8, or 16) for a typical input
channel.
8. If the calculated conversion times are not sufficient, return to step 3. Conversion
time is determined by the following equation:
9. Code the selected PSH, PSL, and PSA values into the prescaler fields of
QACR0.
QCLK high time (in ns)
1000 1
PSH
0.5 PSA
++
()
f
sys(in MHz)
----------------------------------------------------------------------
=
QCLK low time (in ns)
1000 1
PSL
0.5 PSA
–
+
()
f
sys (in MHz)
---------------------------------------------------------------------
=
f
QCLK (in MHz)
1000
=
()
QCLK high time (in ns)
QCLK low time (in ns)
+
-----------------------------------------------------------------------------------------------------------------------------
Conversion time (in
s )
16
Number of input sample cycles
+
f
QCLK(in MHz)
-----------------------------------------------------------------------------------------------
=