參數(shù)資料
型號(hào)： MC68HC05C9ECP
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁(yè)數(shù)： 46/106頁(yè)
文件大?。?/td> 659K
代理商： MC68HC05C9ECP
Capture/Compare Timer
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1
44
Freescale Semiconductor
8.3.2 Timer Status Register
The timer status register (TSR), shown in Figure 8-3, contains flags to signal these conditions:
An active signal on the TCAP pin, transferring the contents of the timer registers to the input
capture registers
A match between the 16-bit counter and the output compare registers, transferring the OLVL bit to
the TCMP pin
A timer roll over from $FFFF to $0000
ICF — Input Capture Flag
The ICF bit is set automatically when an edge of the selected polarity occurs on the TCAP pin. Clear
the ICF bit by reading the timer status register with ICF set and then reading the low byte ($0015) of
the input capture registers. Resets have no effect on ICF.
OCF — Output Compare Flag
The OCF bit is set automatically when the value of the timer registers matches the contents of the
output compare registers. Clear the OCF bit by reading the timer status register with OCF set and then
reading the low byte ($0017) of the output compare registers. Resets have no effect on OCF.
TOF — Timer Overflow Flag
The TOF bit is set automatically when the 16-bit counter rolls over from $FFFF to $0000. Clear the
TOF bit by reading the timer status register with TOF set, and then reading the low byte ($0019) of the
timer registers. Resets have no effect on TOF.
Address:
$0013
Bit 7
654321
Bit 0
Read:
ICF
OCF
TOF
00000
Write:
Reset:
U
00000
= Unimplemented
U = Unaffected
Figure 8-3. Timer Status Register (TSR)
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