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參數(shù)資料
| 型號： | MC68HC05C9ECP |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 56/106頁 |
| 文件大?。?/td> | 659K |
| 代理商： | MC68HC05C9ECP |
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Receive Data In (RDI)
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1
Freescale Semiconductor
53
9.7.2 Address Mark Wakeup
In address mark wakeup, the most significant bit (MSB) in a character is used to indicate whether it is an
address (logic 1) or data (logic 0) character. Sleeping receivers will wake up whenever an address
character is received. Systems using this method for wakeup would set the MSB of the first character of
each message and leave it clear for all other characters in the message. Idle periods may be present
within messages and no idle time is required between messages for this wakeup method.
9.8 Receive Data In (RDI)
Receive data is the serial data that is applied through the input line and the SCI to the internal bus. The
receiver circuitry clocks the input at a rate equal to 16 times the baud rate. This time is referred to as the
RT rate in Figure 9-4 and as the receiver clock in Figure 9-6.
Figure 9-4. SCI Examples of Start Bit Sampling Techniques
The receiver clock generator is controlled by the baud rate register; however, the SCI is synchronized by
the start bit, independent of the transmitter.
Once a valid start bit is detected, the start bit, each data bit, and the stop bit are sampled three times at
RT intervals 8RT, 9RT, and 10RT (1RT is the position where the bit is expected to start), as shown in
Figure 9-5. The value of the bit is determined by voting logic which takes the value of the majority of the
samples. A noise flag is set when all three samples on a valid start bit or data bit or the stop bit do not
agree.
Figure 9-5. SCI Sampling Technique Used on All Bits
1
0000
1
0010
1110
11110
0
NOISE
START
RDI
IDLE
1RT
2RT 3RT
4RT
5RT
6RT 7RT
RT CLOCK EDGES FOR ALL THREE EXAMPLES
16X INTERNAL SAMPLING CLOCK
9RT
8RT
10RT
16RT 1RT
SAMPLES
NEXT BIT
PREVIOUS BIT
RDI
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