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參數(shù)資料
| 型號(hào)： | MC68HC05C9ECP |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 67/106頁 |
| 文件大?。?/td> | 659K |
| 代理商： | MC68HC05C9ECP |
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Functional Description
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1
Freescale Semiconductor
63
When CPHA = 0, the shift clock is the OR of SS with SCK. In this clock phase mode, SS must go high
between successive characters in an SPI message. When CPHA = 1, SS may be left low for several SPI
characters. In cases where there is only one SPI slave MCU, its SS line could be tied to VSS as long as
CPHA = 1 clock modes are used.
10.4 Functional Description
Figure 10-2 shows a block diagram of the serial peripheral interface circuitry. When a master device
transmits data to a slave via the MOSI line, the slave device responds by sending data to the master
device via the master’s MISO line. This implies full duplex transmission with both data out and data in
synchronized with the same clock signal. Thus, the byte transmitted is replaced by the byte received and
eliminates the need for separate transmit-empty and receive-full status bits. A single status bit (SPIF) is
used to signify that the input/output (I/O) operation has been completed.
Figure 10-2. Serial Peripheral Interface Block Diagram
The SPI is double buffered on read, but not on write. If a write is performed during data transfer, the
transfer occurs uninterrupted, and the write will be unsuccessful. This condition will cause the write
collision (WCOL) status bit in the SPSR to be set. After a data byte is shifted, the SPIF flag of the SPSR
is set.
S
6
7
543210
SPE
SPIE
SPI CONTROL REGISTER (SPCR)
MSTR
CPOL
CPHA
SPR1
SPR2
$000A
WCOL
SPIF
SPI STATUS REGISTER (SPSR)
0
MODF
0
$000B
BIT 6
BIT 7
SPI DATA REGISTER (SPDR)
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
$000C
DWOM
00
SPI SHIFT REGISTER
DIVIDER
CLOCK
LOGIC
SPDR ($000C)
7 6 5 4 3 2 1 0
MODF
WCOL
SPIF
SPR1
SPR0
CPOL
CPHA
MSTR
SPE
SPIE
PD3/
MOSI
PD2/
MISO
÷ 2
÷ 32
÷ 16
÷ 4
SELECT
SPI
CONTROL
INTERNAL DATA BUS
MSTR
S
M
INTERNAL
CLOCK
(XTAL
÷2)
SPI CLOCK (MASTER)
SPI INTERRUPT REQUEST
SH
IFT
CL
OCK
PD4/
SCK
PD5/
SS
SLAVE
SPI
MASTER
CLOCK
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