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| 型號： | MC68HC05C9ECP |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 49/106頁 |
| 文件大?。?/td> | 659K |
| 代理商： | MC68HC05C9ECP |
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Timer During Wait Mode
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1
Freescale Semiconductor
47
To prevent OCF from being set between the time it is read and the time the output compare registers are
updated, use this procedure:
1.
Disable interrupts by setting the I bit in the CCR.
2.
Write to OCRH. Compares are now inhibited until OCRL is written.
3.
Clear bit OCF by reading timer status register (TSR).
4.
Enable the output compare function by writing to OCRL.
5.
Enable interrupts by clearing the I bit in the CCR.
8.4 Timer During Wait Mode
The central processor unit (CPU) clock halts during wait mode, but the timer remains active. If interrupts
are enabled, a timer interrupt will cause the processor to exit wait mode.
8.5 Timer During Stop Mode
In stop mode, the timer stops counting and holds the last count value if STOP is exited by an interrupt. If
STOP is exited by reset, the counters are forced to $FFFC. During STOP, if at least one valid input
capture edge occurs at the TCAP pins, the input capture detect circuit is armed. This does not set any
timer flags or wake up the microcontroller unit (MCU). But if an interrupt is used to exit stop mode, there
is an active input capture flag and data from the first valid edge that occurred during the stop mode. If
reset is used to exit stop mode, then no input capture flag or data remains, even if a valid input capture
edge occurred.
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