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參數(shù)資料
| 型號： | MC68HC05C9ECP |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 69/106頁 |
| 文件大小： | 659K |
| 代理商： | MC68HC05C9ECP |
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SPI Registers
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1
Freescale Semiconductor
65
SPIE — Serial Peripheral Interrupt Enable Bit
This read/write bit enables SPI interrupts. Reset clears the SPIE bit.
1 = SPI interrupts enabled
0 = SPI interrupts disabled
SPE — Serial Peripheral System Enable Bit
This read/write bit enables the SPI. Reset clears the SPE bit.
1 = SPI system enabled
0 = SPI system disabled
DWOM — Port D Wire-OR Mode Option Bit
This read/write bit disables the high side driver transistors on port D outputs so that port D outputs
become open-drain drivers. DWOM affects all seven port D pins together.
1 = Port D outputs act as open-drain outputs.
0 = Port D outputs are normal CMOS outputs.
MSTR — Master Mode Select Bit
This read/write bit selects master mode operation or slave mode operation. Reset clears the MSTR bit.
1 = Master mode
0 = Slave mode
CPOL — Clock Polarity Bit
When the clock polarity bit is cleared and data is not being transferred, a steady state low value is
produced at the SCK pin of the master device. Conversely, if this bit is set, the SCK pin will idle high.
This bit is also used in conjunction with the clock phase control bit to produce the desired clock-data
relationship between master and slave. See Figure 10-1.
CPHA — Clock Phase Bit
The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relationship between
master and slave. The CPOL bit can be thought of as simply inserting an inverter in series with the
SCK line. The CPHA bit selects one of two fundamentally different clocking protocols. When
CPHA = 0, the shift clock is the OR of SCK with SS. As soon as SS goes low, the transaction begins
and the first edge on SCK invokes the first data sample. When CPHA=1, the SS pin may be thought
of as a simple output enable control. See Figure 10-1.
SPR1 and SPR0 — SPI Clock Rate Select Bits
These read/write bits select one of four master mode serial clock rates, as shown in Table 10-1. They
have no effect in slave mode.
Table 10-1. SPI Clock Rate Selection
SPR1 and SPR0
SPI Clock Rate
0 0
Internal clock
÷ 2
0 1
Internal clock
÷ 4
1 0
Internal clock
÷ 16
1 1
Internal clock
÷ 32
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