- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄69026 > MC68HC05C9ECP (FREESCALE SEMICONDUCTOR INC) 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 PDF資料下載
參數(shù)資料
| 型號： | MC68HC05C9ECP |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 57/106頁 |
| 文件大小： | 659K |
| 代理商： | MC68HC05C9ECP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁當前第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁
Serial Communications Interface (SCI)
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1
54
Freescale Semiconductor
9.9 Start Bit Detection
When the input (idle) line is detected low, it is tested for three more sample times (referred to as the start
edge verification samples in Figure 9-4). If at least two of these three verification samples detect a logic 0,
a valid start bit has been detected; otherwise, the line is assumed to be idle. A noise flag is set if all three
verification samples do not detect a logic 0. Thus, a valid start bit could be assumed with a set noise flag
present.
If a framing error has occurred without detection of a break (10 0s for 8-bit format or 11 0s for 9-bit format),
the circuit continues to operate as if there actually was a stop bit, and the start edge will be placed
artificially. The last bit received in the data shift register is inverted to a logic 1, and the three logic 1 start
qualifiers (shown in Figure 9-4) are forced into the sample shift register during the interval when detection
of a start bit is anticipated (see Figure 9-6); therefore, the start bit will be accepted no sooner than it is
anticipated.
Figure 9-6. SCI Artificial Start Following a Frame Error
If the receiver detects that a break (RDRF = 1, FE = 1, receiver data register = $003B) produced the
framing error, the start bit will not be artificially induced and the receiver must actually detect a logic 1
before the start bit can be recognized (see Figure 9-7).
Figure 9-7. SCI Start Bit Following a Break
DATA
EXPECTED STOP
DATA SAMPLES
ARTIFICIAL EDGE
START BIT
DATA
RDI
DATA
EXPECTED STOP
DATA SAMPLES
START EDGE
START BIT
DATA
RDI
a) Case 1: Receive Line Low During Artificial Edge
b) Case 2: Receive Line High During Expected Start Edge
EXPECTED STOP
DATA SAMPLES
DETECTED AS VALID START EDGE
START BIT
RDI
BREAK
START
QUALIFIERS
START EDGE
VERIFICATION
SAMPLES
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HC05CC2B | 8-BIT, MROM, 4.2 MHz, MICROCONTROLLER, PDIP42 |
| MC68HC05CJ4FB | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| MC68HC705CJ4FB | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| MC68HC05E0FN | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQCC68 |
| MC68HC05E5P | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC05CT4FB | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification |
| MC68HC05CT4FN | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification |
| MC68HC05D9 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:8-bit microcomputer with PWM outputs and LED drive |
| MC68HC05E0 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit |
| MC68HC05E0FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
發(fā)布緊急采購，3分鐘左右您將得到回復。