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參數(shù)資料
| 型號： | MC68HC05C9ECP |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 48/106頁 |
| 文件大?。?/td> | 659K |
| 代理商： | MC68HC05C9ECP |
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Capture/Compare Timer
MC68HC05C9E Advance Information Data Sheet, Rev. 0.1
46
Freescale Semiconductor
8.3.5 Input Capture Registers
When a selected edge occurs on the TCAP pin, the current high and low bytes of the 16-bit counter are
latched into the input capture registers. Reading ICRH before reading ICRL inhibits further capture until
ICRL is read. Reading ICRL after reading the status register clears the input capture flag (ICF). Writing to
the input capture registers has no effect.
NOTE
To prevent interrupts from occurring between readings of ICRH and ICRL,
set the interrupt flag in the condition code register before reading ICRH, and
clear the flag after reading ICRL.
8.3.6 Output Compare Registers
When the value of the 16-bit counter matches the value in the output compare registers, the planned
TCMP pin action takes place. Writing to OCRH before writing to OCRL inhibits timer compares until OCRL
is written. Reading or writing to OCRL after the timer status register clears the output compare flag (OCF).
Address:
$0014 — ICRH
Bit 7
654321
Bit 0
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
Unaffected by reset
Address:
$0015 — ICRL
Bit 7
65432
1
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
Unaffected by reset
= Unimplemented
Figure 8-6. Input Capture Registers (ICRH and ICRL)
Address:
$0016 — OCRH
Bit 7
654321
Bit 0
Write:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Read:
Reset:
Unaffected by reset
Address:
$0017 — OCRL
Bit 7
654321
Bit 0
Write:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read:
Reset:
Unaffected by reset
Figure 8-7. Output Compare Registers (OCRH and OCRL)
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