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參數(shù)資料
| 型號： | MC68HC05LJ5P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 24/81頁 |
| 文件大?。?/td> | 905K |
| 代理商： | MC68HC05LJ5P |
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GENERAL RELEASE SPECIFICATION
November 10, 1998
MOTOROLA
INTERRUPTS
MC68HC05LJ5
4-4
REV 1
PA7 interrupt is not used. As long as the output state of the IRQF ag bit is active
the CPU will continuously re-enter the IRQ interrupt sequence until the active
state is removed or the IRQE enable bit is cleared.
4.5.2 PA7 Pin
PA7 interrupt source, if enabled by IRQE1 enable bit, triggers IRQ interrupt on
PA7 falling edge only. The IRQ1 latch (IRQF1 ag) can ONLY be cleared by writing
a logic one to the IRQR1 acknowledge bit in the ICSR. IRQ vector fetch can NOT
clear IRQF1 ag. IRQ interrupt caused by PA7 falling edge also vectors to $0FFA
and $0FFB.
4.5.3 IRQ Control/Status Register (ICSR), $0A
The IRQ interrupt function is controlled by the ICSR located at $000A. All unused
bits in the ICSR will read as logic zeros. The IRQF, IRQF1, IRQE1 bits are cleared
and IRQE bit is set by reset.
Figure 4-2. IRQ Status & Control Register
IRQR 1 - PA7 Interrupt Acknowledge
The IRQR1 acknowledge bit clears an IRQ interrupt triggered by a falling edge
on PA7 by clearing the IRQ1 latch. The IRQR1 acknowledge bit will always read
as a logic zero.
1 =
Writing a logic one to the IRQR1 acknowledge bit will clear the IRQ1
latch.
0 =
Writing a logic zero to the IRQR1 acknowledge bit will have no effect
on the IRQ1 latch.
IRQR - IRQ Interrupt Acknowledge
The IRQR acknowledge bit clears an IRQ interrupt by clearing the IRQ latch.
The IRQR acknowledge bit will always read as a logic zero.
1 =
Writing a logic one to the IRQR acknowledge bit will clear the IRQ
latch.
0 =
Writing a logic zero to the IRQR acknowledge bit will have no effect
on the IRQ latch.
0
IRQR1
ICSR
$000A
1
7
W
R
0000000
reset
6543210
IRQE
IRQF
0
IRQR
0
IRQF1
IRQE1
0
RESERVED FOR TEST
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